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Digital FM Receiver: S.KARTHIK D.E.E.E.,D.I.S.,B.E

The document describes the design of a digital FM receiver using VHDL that utilizes a phase locked loop (PLL) as the main component to demodulate FM signals. The PLL-based digital FM receiver architecture consists of a phase detector, loop filter, voltage controlled oscillator/numerical controlled oscillator, and aims to optimize the design to minimize gate count and area. The document outlines the working principle, block diagram, and design flow of the digital FM receiver project.

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Tushar Goel
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83 views21 pages

Digital FM Receiver: S.KARTHIK D.E.E.E.,D.I.S.,B.E

The document describes the design of a digital FM receiver using VHDL that utilizes a phase locked loop (PLL) as the main component to demodulate FM signals. The PLL-based digital FM receiver architecture consists of a phase detector, loop filter, voltage controlled oscillator/numerical controlled oscillator, and aims to optimize the design to minimize gate count and area. The document outlines the working principle, block diagram, and design flow of the digital FM receiver project.

Uploaded by

Tushar Goel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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DIGITAL FM RECEIVER

S.KARTHIK D.E.E.E.,D.I.S.,B.E.
Aim Of the Project

 To develop a Digital FM receiver using


VHDL.
 To optimize the design of PLL and
NCOs.
 To minimize the gate count and area.
Introduction

 FM signals can be demodulated using


various techniques such as, Differentiator
and Envelope Detector, Zero Crossing
Detector, Phase Lock Loop (PLL).

 The design of the Digital FM Receiver


circuit in this project uses Phase Locked
Loop (PLL) as the main core.
PLL
PLL demodulators are widely used in
today’s communication systems
because of their superior performance,
ease of alignment, and ease of
implementation using inexpensive
integrated circuits.

If PLL is locked to a FM signal, the


VCO tracks the instantaneous frequency
of the input signal.
Working Principle

 Frequency modulated input signal is


assumed as a series of numerical values
(digital signal) via 8-bit of analog to digital
conversion (ADC) circuit.

 The FM Receiver gets the 8 bit signal every


clock cycle and outputs the demodulated
signal.
Architecture Description

 The system of Digital FM Receiver consists of a


digital PLL cascaded with digital low pass filter.
 The important blocks in the Digital FM receiver
are,
Phase detector.
A Low pass filter.
An Error amplifier.
A VCO/ NCO.
Block Diagram
Phase Detector

 Phase detector compares the phase and


frequency of the incoming signal to that of
the output of the VCO/NCO.
 If the two signals differ in frequency an
error voltage is generated.
 It is basically a multiplier.
Loop Filter

 Loop filter will remove the high frequency


component.
 The difference frequency component is
amplified and then applied as control
voltage to the VCO.
VCO
 A voltage-controlled oscillator or VCO is
an electronic oscillator designed to be
controlled in oscillation frequency by a
voltage input.
 It is a free running oscillator and operates at
a set of frequency.
 It can be shifted to either side by applying a
DC control voltage.
NCO
 A numerically controlled oscillator (NCO) or
digitally controlled oscillator (DCO) is an
electronic system for synthesizing a range of
frequencies.
 DCOs have been used as cheap replacements for
VCOs.

 Numerical Controlled Oscillator (NCO) will take the


corrective error voltage, and then shift its output
frequency from its free-running value to the input
signal frequency and thus keep the PLL in lock.
Merits

 NCOs are phase continuous and are better


than VCOs.
 Since the NCO is highly linear, it is possible
to realize high linear FM demodulators.
Applications

 With the advanced technology, FM


detectors using PLL are widely used in
various FM communication systems.
Design Flow
HDL to be used

VHDL-93(IEEE Std. 1076-1993) or


VERILOG(IEEE Std. 1364).
FPGA to be used

 ALTERA CYCLONE II. (or)


 XILINX SPARTAN II XC2S200.
Works done

 Collected related materials.


 Attended ALTERA demo.
Future works
 Algorithmic Survey.
 To optimized the multiplication operation
used in the phase detector component.
 Develop HDL coding.
 Functional simulation and logic verification.
 Synthesis.
 Implementation on FPGA.
 Backend if possible.
References

 Michel. C. Jeruchim- Simulation Of


Communication Systems Modeling,
Methodology and Techniques.
 Simon Haykin – Communication Systems.
 D. Roy Choudhury – Linear Integrated Circuits.
Suggestions, if any?
Thank u for Ur suggestions

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