Microprocessor - Interfacing

Interface
• Interface is the path for communication
between two components.
• Interfacing is of two types
o memory interfacing and
o I/O interfacing
 Memory Interfacing
• When executing any instruction, one need the
microprocessor to access the memory for reading
instruction codes and the data stored in the memory
• For this, both the memory and the microprocessor
requires some signals to read from and write to
registers
• The interfacing process includes some key factors to
match with the memory requirements and
microprocessor signals
• The interfacing circuit therefore should be designed in
such a way that it matches the memory signal
requirements with the signals of the microprocessor
 IO Interfacing
• There are various communication devices like
the keyboard, mouse, printer, etc.
• Interfacing the keyboard and other devices
with the microprocessor by using latches and
buffers
• This type of interfacing is known as I/O
interfacing
 8085 Interfacing Pins
• Following is the list of 8085 pins used for
interfacing with other devices −
o A15 - A8 (Higher Address Bus)
o AD7 - AD0(Lower Address/Data Bus)
o ALE
o RD
o WR
o READY
 Ways of Communication −
Microprocessor with the Outside
World?
• There are two ways of communication in which the
microprocessor can connect with the outside world.
• Serial Communication Interface
o In this type of communication, the interface gets a single
byte of data from the microprocessor and sends it bit by bit
to the other system serially and vice-a-versa.
• Parallel Communication Interface
o In this type of communication, the interface gets a byte of
data from the microprocessor and sends it bit by bit to the
other systems in simultaneous (or) parallel fashion and
vice-a versa.
 8279 - Programmable Keyboarrd
• 8279 programmable keyboard/display
controller is designed by Intel that interfaces a
keyboard with the CPU.
• The keyboard first scans the keyboard and
identifies if any key has been pressed.
• It then sends their relative response of the
pressed key to the CPU and vice-a-versa
 8279 - Programmable Keyboarrd
• How Many Ways the Keyboard is Interfaced
with the CPU?
o The Keyboard can be interfaced either in the
interrupt or the polled mode.
 In the Interrupt mode, the processor is requested
service only if any key is pressed, otherwise the CPU
will continue with its main task.
 In the Polled mode, the CPU periodically reads an
internal flag of 8279 to check whether any key is
pressed or not with key pressure.
 8279 - Programmable Keyboarrd
• How Does 8279 Keyboard Work?
o The keyboard consists of maximum 64 keys, which are
interfaced with the CPU by using the key-codes.
o These key-codes are de-bounced and stored in an 8-byte FIFO
RAM, which can be accessed by the CPU
o If more than 8 characters are entered in the FIFO, then it means
more than eight keys are pressed at a time
o This is when the overrun status is set.
o If a FIFO contains a valid key entry, then the CPU is interrupted
in an interrupt mode else the CPU checks the status in polling to
read the entry
o Once the CPU reads a key entry, then FIFO is updated, and the
key entry is pushed out of the FIFO to generate space for new
entries.
 8279 - Programmable Keyboarrd
• Architecture
 8279 - Programmable Keyboarrd
• I/O Control and Data Buffer
o This unit controls the flow of data through the
microprocessor
o It is enabled only when D is low. Its data buffer
interfaces the external bus of the system with the
internal bus of the microprocessor
o The pins A0, RD, and WR are used for command,
status or data read/write operations.
 8279 - Programmable Keyboarrd
• Control and Timing Register and Timing
Control
o This unit contains registers to store the keyboard,
display modes, and other operations as
programmed by the CPU
o The timing and control unit handles the timings for
the operation of the circuit
 8279 - Programmable Keyboarrd
• Scan Counter
o It has two modes i.e. Encoded mode and Decoded
mode
o In the encoded mode, the counter provides the
binary count that is to be externally decoded to
provide the scan lines for the keyboard and display
o In the decoded scan mode, the counter internally
decodes the least significant 2 bits and provides a
decoded 1 out of 4 scan on SL0-SL3.
 8279 - Programmable Keyboarrd
• Return Buffers, Keyboard Debounce, and
Control
o This unit first scans the key closure row-wise, if
found then the keyboard debounce unit debounces
the key entry
o In case, the same key is detected, then the code of
that key is directly transferred to the sensor RAM
along with SHIFT & CONTROL key status.
 8279 - Programmable Keyboarrd
• FIFO/Sensor RAM and Status Logic
o This unit acts as 8-byte first-in-first-out (FIFO) RAM
where the key code of every pressed key is entered
into the RAM as per their sequence.
o The status logic generates an interrupt request after
each FIFO read operation till the FIFO gets empty.
o In the scanned sensor matrix mode, this unit acts as
sensor RAM where its each row is loaded with the
status of their corresponding row of sensors into the
matrix
o When the sensor changes its state, the IRQ line
changes to high and interrupts the CPU.
 8279 - Programmable Keyboarrd
• Display Address Registers and Display RAM
o This unit consists of display address registers
which holds the addresses of the word currently
read/written by the CPU to/from the display RAM
 8279 - Programmable Keyboarrd
• 8279 − Pin Description
 8279 - Programmable Keyboarrd
• 8279 − Pin Description
o Data Bus Lines, DB0 - DB7
 These are 8 bidirectional data bus lines used to transfer the
data to/from the CPU
o CLK
 The clock input is used to generate internal timings required
by the microprocessor
o RESET
 As the name suggests this pin is used to reset the
microprocessor
o CS Chip Select
 When this pin is set to low, it allows read/write operations,
else this pin should be set to high.
 8279 - Programmable Keyboarrd
• 8279 − Pin Description
• A0
o This pin indicates the transfer of command/status information.
When it is low, it indicates the transfer of data.
• RD, WR
o This Read/Write pin enables the data buffer to send/receive data
over the data bus.
• IRQ
o This interrupt output line goes high when there is data in the
FIFO sensor RAM. The interrupt line goes low with each FIFO
RAM read operation. However, if the FIFO RAM further
contains any key-code entry to be read by the CPU, this pin
again goes high to generate an interrupt to the CPU.
 8279 - Programmable Keyboarrd
• 8279 − Pin Description
o Vss, Vcc
 These are the ground and power supply lines of the
microprocessor
o SL0 − SL3
 These are the scan lines used to scan the keyboard matrix and
display the digits. These lines can be programmed as encoded
or decoded, using the mode control register.
o RL0 − RL7
 These are the Return Lines which are connected to one
terminal of keys, while the other terminal of the keys is
connected to the decoded scan lines. These lines are set to 0
when any key is pressed.
 8279 - Programmable Keyboarrd
• 8279 − Pin Description
o SHIFT
 The Shift input line status is stored along with every key
code in FIFO in the scanned keyboard mode.
 Till it is pulled low with a key closure, it is pulled up
internally to keep it high
o CNTL/STB - CONTROL/STROBED I/P Mode
 In the keyboard mode, this line is used as a control input and
stored in FIFO on a key closure
 The line is a strobe line that enters the data into FIFO RAM,
in the strobed input mode
 It has an internal pull up. The line is pulled down with a key
closure.
 8279 - Programmable Keyboarrd
• 8279 − Pin Description
o BD
 It stands for blank display. It is used to blank the display
during digit switching.
o OUTA0 – OUTA3 and OUTB0 – OUTB3
 These are the output ports for two 16x4 or one 16x8
internal display refresh registers
 The data from these lines is synchronized with the scan
lines to scan the display and the keyboard.
 8279 - Programmable Keyboarrd
• Operational Modes of 8279
o There are two modes of operation on 8279 Input
Mode and Output Mode.
 8279 - Programmable Keyboarrd
• Operational Modes of 8279 – Input Mode
o This mode deals with the input given by the keyboard and this mode is
further classified into 3 modes.
o Scanned Keyboard Mode
 In this mode, the key matrix can be interfaced using either encoded or decoded scans
 In the encoded scan, an 8×8 keyboard or in the decoded scan, a 4×8 keyboard can be
interfaced
 The code of key pressed with SHIFT and CONTROL status is stored into the FIFO
RAM.
o Scanned Sensor Matrix
 In this mode, a sensor array can be interfaced with the processor using either encoder or
decoder scans
 In the encoder scan, 8×8 sensor matrix or with decoder scan 4×8 sensor matrix can be
interfaced.
o Strobed Input
 In this mode, when the control line is set to 0, the data on the return lines is stored in the
FIFO byte by byte.
 8279 - Programmable Keyboarrd
• Operational Modes of 8279 – Output Mode
o This mode deals with display-related operations
o This mode is further classified into two output
modes.
o Display Scan
 This mode allows 8/16 character multiplexed displays to
be organized as dual 4-bit/single 8-bit display units.
o Display Entry
 This mode allows the data to be entered for display
either from the right side/left side.
 8257 DMA Controller
• DMA stands for Direct Memory Access.
• It is designed by Intel to transfer data at the fastest rate
• It allows the device to transfer the data directly to/from
memory without any interference of the CPU
• Using a DMA controller, the device requests the CPU
to hold its data, address and control bus, so the device
is free to transfer data directly to/from the memory
• The DMA data transfer is initiated only after receiving
HLDA signal from the CPU.
 8257 DMA Controller
• How DMA Operations are Performed?
o Following is the sequence of operations performed by
a DMA −
 Initially, when any device has to send data between the
device and the memory, the device has to send DMA request
(DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU
and waits for the CPU to assert the HLDA.
 Then the microprocessor tri-states all the data bus, address
bus, and control bus. The CPU leaves the control over bus
and acknowledges the HOLD request through HLDA signal.
 Now the CPU is in HOLD state and the DMA controller has
to manage the operations over buses between the CPU,
memory, and I/O devices.
 8257 DMA Controller
• Features of 8257
o It has four channels which can be used over four I/O devices.
o Each channel has 16-bit address and 14-bit counter.
o Each channel can transfer data up to 64kb.
o Each channel can be programmed independently.
o Each channel can perform read transfer, write transfer and verify
transfer operations.
o It generates MARK signal to the peripheral device that 128 bytes
have been transferred.
o It requires a single phase clock.
o Its frequency ranges from 250Hz to 3MHz.
o It operates in 2 modes, i.e., Master mode and Slave mode.
 8257 DMA Controller

• 8257 Architecture
 8257 DMA Controller
• 8257 Pin Description
 8257 DMA Controller
• DRQ0−DRQ3
o These are the four individual channel DMA request
inputs, which are used by the peripheral devices for
using DMA services. When the fixed priority mode is
selected, then DRQ0 has the highest priority and
DRQ3 has the lowest priority among them.
• DACKo − DACK3
o These are the active-low DMA acknowledge lines,
which updates the requesting peripheral about the
status of their request by the CPU. These lines can also
act as strobe lines for the requesting devices.
 8257 DMA Controller
• Do − D7
o These are bidirectional, data lines which are used to
interface the system bus with the internal data bus of DMA
controller. In the Slave mode, it carries command words to
8257 and status word from 8257. In the master mode, these
lines are used to send higher byte of the generated address
to the latch. This address is further latched using ADSTB
signal.
• IOR
o It is an active-low bidirectional tri-state input line, which is
used by the CPU to read internal registers of 8257 in the
Slave mode. In the master mode, it is used to read data
from the peripheral devices during a memory write cycle.
 8257 DMA Controller
• IOW
o It is an active low bi-direction tri-state line, which is used
to load the contents of the data bus to the 8-bit mode
register or upper/lower byte of a 16-bit DMA address
register or terminal count register. In the master mode, it is
used to load the data to the peripheral devices during DMA
memory read cycle.
• CLK
o It is a clock frequency signal which is required for the
internal operation of 8257.
• RESET
o This signal is used to RESET the DMA controller by
disabling all the DMA channels.
 8257 DMA Controller
• Ao - A3
o These are the four least significant address lines. In the slave
mode, they act as an input, which selects one of the registers to
be read or written. In the master mode, they are the four least
significant memory address output lines generated by 8257.
• CS
o It is an active-low chip select line. In the Slave mode, it enables
the read/write operations to/from 8257. In the master mode, it
disables the read/write operations to/from 8257.
• A4 - A7
o These are the higher nibble of the lower byte address generated
by DMA in the master mode.
 8257 DMA Controller
• READY
o It is an active-high asynchronous input signal, which makes
DMA ready by inserting wait states.
• HRQ
o This signal is used to receive the hold request signal from
the output device. In the slave mode, it is connected with a
DRQ input line 8257. In Master mode, it is connected with
HOLD input of the CPU.
• HLDA
o It is the hold acknowledgement signal which indicates the
DMA controller that the bus has been granted to the
requesting peripheral by the CPU when it is set to 1.
 8257 DMA Controller
• MEMR
o It is the low memory read signal, which is used to read the
data from the addressed memory locations during DMA
read cycles.
• MEMW
o It is the active-low three state signal which is used to write
the data to the addressed memory location during DMA
write operation.
• ADST
o This signal is used to convert the higher byte of the
memory address generated by the DMA controller into the
latches.
 8257 DMA Controller
• AEN
o This signal is used to disable the address bus/data bus.
• TC
o It stands for ‘Terminal Count’, which indicates the present DMA
cycle to the present peripheral devices.
• MARK
o The mark will be activated after each 128 cycles or integral
multiples of it from the beginning. It indicates the current DMA
cycle is the 128th cycle since the previous MARK output to the
selected peripheral device.
• Vcc
o It is the power signal which is required for the operation of the
circuit.
 8255A - Programmable Peripheral
Interface
• The 8255A is a general purpose programmable
I/O device designed to transfer the data from
I/O to interrupt I/O under certain conditions as
required.
• It can be used with almost any microprocessor.
• It consists of three 8-bit bidirectional I/O ports
(24I/O lines) which can be configured as per
the requirement.
 8255A - Programmable Peripheral
Interface
• Ports of 8255A
o 8255A has three ports, i.e., PORT A, PORT B, and PORT C.
o Port A contains one 8-bit output latch/buffer and one 8-bit input
buffer.
o Port B is similar to PORT A.
o Port C can be split into two parts, i.e. PORT C lower (PC0-PC3)
and PORT C upper (PC7-PC4) by the control word.
o These three ports are further divided into two groups, i.e. Group
A includes PORT A and upper PORT C. Group B includes PORT
B and lower PORT C. These two groups can be programmed in
three different modes, i.e. the first mode is named as mode 0, the
second mode is named as Mode 1 and the third mode is named
as Mode 2.
 8255A - Programmable Peripheral
Interface
• Operating Modes, 8255A has three different operating modes −
• Mode 0 − In this mode, Port A and B is used as two 8-bit ports and
Port C as two 4-bit ports. Each port can be programmed in either
input mode or output mode where outputs are latched and inputs are
not latched. Ports do not have interrupt capability.
• Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They
can be configured as either input or output ports. Each port uses
three lines from port C as handshake signals. Inputs and outputs are
latched.
• Mode 2 − In this mode, Port A can be configured as the bidirectional
port and Port B either in Mode 0 or Mode 1. Port A uses five signals
from Port C as handshake signals for data transfer. The remaining
three signals from Port C can be used either as simple I/O or as
handshake for port B.
 8255A - Programmable Peripheral
Interface
• Features of 8255A
• The prominent features of 8255A are as
follows −
o It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
o Address/data bus must be externally demux'd.
o It is TTL compatible.
o It has improved DC driving capability.
8255A - Programmable Peripheral Interface

• 8255 Architecture
 8255A - Programmable Peripheral
Interface
Intel 8255A - Pin
Description
 8255A - Programmable Peripheral
Interface
• Data Bus Buffer
o It is a tri-state 8-bit buffer, which is used to interface
the microprocessor to the system data bus
o Data is transmitted or received by the buffer as per the
instructions by the CPU
o Control words and status information is also
transferred using this bus.
• Read/Write Control Logic
o This block is responsible for controlling the internal/
external transfer of data/control/status word. It accepts
the input from the CPU address and control buses, and
in turn issues command to both the control groups.
 8255A - Programmable Peripheral
Interface
• CS
o It stands for Chip Select
o A LOW on this input selects the chip and enables
the communication between the 8255A and the
CPU
o It is connected to the decoded address, and A0 &
A1 are connected to the microprocessor address
lines.
 8255A - Programmable Peripheral
Interface
• Their result depends on the following
conditions −

CS A1 A0 Result
0 0 0 PORT A
0 0 1 PORT B
0 1 0 PORT C
0 1 1 Control Register
1 X X No Selection
 8255A - Programmable Peripheral
Interface
• WR
o It stands for write
o This control signal enables the write operation
o When this signal goes low, the microprocessor writes into a
selected I/O port or control register.
• RESET
o This is an active high signal
o It clears the control register and sets all ports in the input mode.
• RD
o It stands for Read
o This control signal enables the Read operation
o When the signal is low, the microprocessor reads the data from
the selected I/O port of the 8255.
 8255A - Programmable Peripheral
Interface
• A0 and A1
o These input signals work with RD, WR, and one of
the control signal
• Following is the table showing their various
signals with their result.
A1 A0 RD WR CS Result
Input Operation
0 0 0 1 0
PORT A → Data Bus
0 1 0 1 0 PORT B → Data Bus
1 0 0 1 0 PORT C → Data Bus
Output Operation
0 0 1 0 0
Data Bus → PORT A
0 1 1 0 0 Data Bus → PORT A
1 0 1 0 0 Data Bus → PORT B
1 1 1 0 0 Data Bus → PORT D
 8253 - Programmable Interval Timer
• The Intel 8253 and 8254 are Programmable
Interval Timers (PTIs) designed for
microprocessors to perform timing and counting
functions using three 16-bit registers. Each
counter has 2 input pins, i.e. Clock & Gate, and 1
pin for “OUT” output
• To operate a counter, a 16-bit count is loaded in
its register
• On command, it begins to decrement the count
until it reaches 0, then it generates a pulse that can
be used to interrupt the CPU.
 8253 - Programmable Interval Timer
• Difference between 8253 and 8254
o The following table differentiates the features of
8253 and 8254 −
8253 8254
Its operating frequency is 0 - 2.6 Its operating frequency is 0 - 10
MHz MHz
It uses N-MOS technology It uses H-MOS technology
Read-Back command is not Read-Back command is
available available
Reads and writes of the same Reads and writes of the same
counter cannot be interleaved. counter can be interleaved.
 8253 - Programmable Interval Timer
• Features of 8253 / 54
o The most prominent features of 8253/54 are as follows
−
o It has three independent 16-bit down counters.
o It can handle inputs from DC to 10 MHz.
o These three counters can be programmed for either
binary or BCD count.
o It is compatible with almost all microprocessors.
o 8254 has a powerful command called READ BACK
command, which allows the user to check the count
value, the programmed mode, the current mode, and
the current status of the counter.
 8253 - Programmable Interval Timer
• 8254 Architecture
 8253 - Programmable Interval Timer
• 8254 Pin Description
 8253 - Programmable Interval Timer
• In the above figure, there are three counters, a
data bus buffer, Read/Write control logic, and
a control register
• Each counter has two input signals - CLOCK
& GATE, and one output signal - OUT.
 8253 - Programmable Interval Timer
• Data Bus Buffer
o It is a tri-state, bi-directional, 8-bit buffer, which is
used to interface the 8253/54 to the system data
bus
o It has three basic functions −
 Programming the modes of 8253/54.
 Loading the count registers.
 Reading the count values.
 8253 - Programmable Interval Timer
• Read/Write Logic
o It includes 5 signals, i.e. RD, WR, CS, and the address
lines A0 & A1.
o In the peripheral I/O mode, the RD and WR signals are
connected to IOR and IOW, respectively
o In the memory mapped I/O mode, these are connected
to MEMR and MEMW.
o Address lines A0 & A1 of the CPU are connected to
lines A0 and A1 of the 8253/54, and CS is tied to a
decoded address
o The control word register and counters are selected
according to the signals on lines A0 & A1.
8253 - Programmable Interval Timer

A1 A0 Result

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control Word Register

X X No Selection
 8253 - Programmable Interval Timer
• Control Word Register
o This register is accessed when lines A0 & A1 are at
logic 1.
o It is used to write a command word, which
specifies the counter to be used, its mode, and
either a read or write operation.
o Following table shows the result for various
control inputs.
8253 - Programmable Interval Timer
A1 A0 RD WR CS Result
0 0 1 0 0 Write Counter 0

0 1 1 0 0 Write Counter 1

1 0 1 0 0 Write Counter 2

1 1 1 0 0 Write Control Word

0 0 0 1 0 Read Counter 0

0 1 0 1 0 Read Counter 1

1 0 0 1 0 Read Counter 2

1 1 0 1 0 No operation

X X 1 1 0 No operation

X X X X 1 No operation
 8253 - Programmable Interval Timer
• Counters
o Each counter consists of a single, 16 bit-down
counter, which can be operated in either binary or
BCD
o Its input and output is configured by the selection
of modes stored in the control word register.
o The programmer can read the contents of any of
the three counters without disturbing the actual
count in process
 8253 - Programmable Interval Timer
• Operational Modes
• 8253/54 can be operated in 6 different modes
• Mode 0 ─ Interrupt on Terminal Count
o It is used to generate an interrupt to the microprocessor after a
certain interval.
o Initially the output is low after the mode is set. The output
remains LOW after the count value is loaded into the counter.
o The process of decrementing the counter continues till the
terminal count is reached, i.e., the count become zero and the
output goes HIGH and will remain high until it reloads a new
count.
o The GATE signal is high for normal counting. When GATE goes
low, counting is terminated and the current count is latched till
the GATE goes high again.
 8253 - Programmable Interval Timer
• Operational Modes
• 8253/54 can be operated in 6 different modes
• Mode 1 – Programmable One Shot
o It can be used as a mono stable multi-vibrator.
o The gate input is used as a trigger input in this
mode.
o The output remains high until the count is loaded
and a trigger is applied.
 8253 - Programmable Interval Timer
• Operational Modes
• 8253/54 can be operated in 6 different modes
• Mode 2 – Rate Generator
o The output is normally high after initialization.
o Whenever the count becomes zero, another low
pulse is generated at the output and the counter
will be reloaded.
 8253 - Programmable Interval Timer
• Operational Modes
• 8253/54 can be operated in 6 different modes
• Mode 3 – Square Wave Generator
o This mode is similar to Mode 2 except the output
remains low for half of the timer period and high
for the other half of the period.
 8253 - Programmable Interval Timer
• Operational Modes
• 8253/54 can be operated in 6 different modes
• Mode 4 − Software Triggered Mode
o In this mode, the output will remain high until the
timer has counted to zero, at which point the output
will pulse low and then go high again.
o The count is latched when the GATE signal goes
LOW.
o On the terminal count, the output goes low for one
clock cycle then goes HIGH. This low pulse can be
used as a strobe.
 8253 - Programmable Interval Timer
• Operational Modes
• 8253/54 can be operated in 6 different modes
• Mode 5 – Hardware Triggered Mode
o This mode generates a strobe in response to an externally
generated signal.
o This mode is similar to mode 4 except that the counting is
initiated by a signal at the gate input, which means it is
hardware triggered instead of software triggered.
o After it is initialized, the output goes high.
o When the terminal count is reached, the output goes low for
one clock cycle.