Chapter 6 Logic Families

Prof.
Robinson Paul ,BVM Engineering College

4/13/2012 ,V.V.Nagar. 1
GTU Dec-2010 Questions
(1) With neat circuit explain the two inputs TTL NAND gate
using TOTAM POLE output also mention the advantages and
disadvantages of TOTAM POLE output.
(2) Define the following terms: :
(1) Input bias current (2) Input offset voltage (3) PSRR (4)Noise margin
(5) fan-in (6) Propagation delay (7)Figure of merit for logic families
(3) Describe the comparison of IC logic families.
(4) Explain with neat circuit diagram Tristate TTL devices.
Prof.Robinson Paul ,BVM Engineering College

4/13/2012 ,V.V.Nagar. 2
GTU June-2010 Questions
1. Give the classification of Logic families. Also list the characteristics of

digital IC and explain any three of them
2. List the logic family. Give comparisons of each of them. Also give the
advantages and disadvantages of each logic families.

4/13/2012 ,V.V.Nagar. 3
GTU June-2011 Questions
1. Define following parameters.

I) Fan-out, II) Propagation delay, III) Speed power product, IV) Slew rate,
V) CMRR, VI) Gain bandwidth product, VII) Power dissipation.
2. Give the comparison between various logic families.

4/13/2012 ,V.V.Nagar. 4
TOPIC 01
Classification based on circuit complexity
SSI: (3 to 30 gates/chip)
The first integrated circuits held only a few devices, perhaps as many as ten diodes,
transistors, resistors and capacitors, making it possible to fabricate one or more logic gates
on a single device. Now known retrospectively as small-scale integration (SSI)
MSI: (30 to 300 gates/chip)
improvements in technique led to devices with hundreds of logic gates, known as medium-
scale integration (MSI).
LSI: (300 to 3,000 gates/chip.)
Further improvements led to large-scale integration (LSI), i.e. systems with at least a
thousand logic gates
VLSI: (more than 3,000 gates/chip)
Very-large-scale integration (VLSI) is the process of creating integrated circuits by
combining thousands of transistors into a single chip
ULSI:
At one time, there was an effort to name and calibrate various levels of large-scale
integration
4/13/2012
above VLSI. Terms like ultra-large-scale integration (ULSI) were used.
,V.V.Nagar. 5
TOPIC 01
Classification based on circuit complexity
Complexity Number of Gates

Small-scale integration(SSI) Fewer than 12
2 3
Medium-scale integration(MSI) 12 to 99 (10 - 10 )
3 5
Large-scale integration(LSI) 100 to 9,999 (10 - 10 )
5 7
Very large-scale integration(VLSI) 10,000 to 99,999 (10 - 10 )
7 9
Ultra large-scale integration(ULSI) 100,000 to 999,999 (10 - 10 )
9 11
Giga-scale integration(GSI) 1,000,000 or more (10 - 10 )
12
Tera-scale integration(TSI) (10 or more)
4/13/2012 ,V.V.Nagar. 6
Ques: 2 Various Logic Families
(A)Bipolar transistors :
 (1) Saturated : RTL,DTL,DCTL,I2L,HTL,TTL

(2)Unsaturated: Schottky TTL and ECL
(B) Unipolar MOSFET transistors : NMOS, PMOS, and CMOS

4/13/2012 ,V.V.Nagar. 7
Ques: 3 Important characteristics of each of IC
families
 3.1 Current and Voltage Parameters :
 VIH (min) : high- level input voltage
 VIL (max) : low- level input voltage
 VOH (min) : high- level output voltage
 VOL (max) : low- level output voltage
 IIH : high- level input current
 IIL : low- level input current
 IOH : high- level output current
 IOL : low- level output current

4/13/2012 ,V.V.Nagar. 8
Ques: 3 Important characteristics of each of IC
families

4/13/2012 ,V.V.Nagar. 9
 VCC: The voltage applied to the power pins.
 VT (Threshold Voltage): The voltage level at which input
pins will transition from being in one state to another.
 VIH (Voltage Input HIGH): Minimum positive voltage
applied to an input pin which will be considered by the
device as a logic HIGH.
 VIL (Voltage Input LOW): Maximum positive voltage
applied to an input pin which will be considered by the
device as a logic LOW.
 VOH (Voltage Output HIGH): Minimum positive voltage
from an output pin which will be considered by the device
as a logic HIGH
4/13/2012 ,V.V.Nagar. 10
 VOL (Voltage Output LOW):Maximum positive voltage

from an output pin which will be considered by the device
as a logic LOW.
 IOH (Current Output HIGH): Current flowing into an
output pin in the logical HIGH state under specified load
conditions.
 IOL (Current Output LOW): Current flowing into an
output pin in the logical LOW state under specified load
conditions.
 IIH (Current Input HIGH): Current flowing into an input
pin when HIGH is applied to that input.
 IIL (Current Input LOW): Current flowing into an input
pin when LOW is applied to that input.
4/13/2012 ,V.V.Nagar. 11
Voltage
Paramete 74 74S 74LS 74AS 74ALS 74F HC HCT AHC
rs
VOH(min) 2.4 2.7 2.7 2.5 2.5 2.5 4.9 4.9 4.4
VOL(max) 0.4 0.5 0.5 0.5 0.5 0.5 0.1 0.1 0.44
VIH(min) 2.0 2.0 2.0 2.0 2.0 2.0 3.5 2.0 3.85
VIL(max) 0.8 0.8 0.8 0.8 0.8 0.8 1.0 0.8 1.65

4/13/2012 ,V.V.Nagar. 12
Ques: 3 Important characteristics of each of IC families
 3.3 Noise Margin:

4/13/2012 ,V.V.Nagar. 13
Sinking and Sourcing
 Output gates are just like any other gate, they can have current flowing in two
directions:
 into the output node (sinking),
 out of the output node (sourcing).
 We can show the output of a gate circuit as being a double-throw switch, that can
connect the output terminal to either VCC or GND, depending on the position of the
switch. For a gate outputting a LOW logic level, the output is analogous to the
following circuit:

4/13/2012 ,V.V.Nagar. 14
 Output gates are just like any other gate, they can have current flowing in two
directions:
 into the output node (sinking),
 out of the output node (sourcing).
 We can show the output of a gate circuit as being a double-throw switch, that can
connect the output terminal to either VCC or GND, depending on the position of the
switch. For a gate outputting a LOW logic level, the output is analogous to the
following Fig 1 & gate outputting a HIGH logic level, the output is analogous to the
following Fig 2

4/13/2012
Figure : 1 ,V.V.Nagar.
Figure :2 15
Figure : 1

4/13/2012 ,V.V.Nagar. 16
Figure : 2

4/13/2012 ,V.V.Nagar. 17
Sinking Sourcing
Figure : 1 Figure : 2
The combination of Q3 and Q4 working as a push-pull transistor

pair has the ability to either source current from VCC via the
output terminal and into a load, or to sink current to GND via
the output terminal from a load.
4/13/2012 ,V.V.Nagar. 18
Sinking and Sourcing Summarize
•The expressions sink and source relate to currents only and they refer to which direction
the current is flowing.
•It is important to remember that logic gates can source and sink a very limited amount of
current, usually in the order of a few mA. Therefore, outputs taken directly from logic
gates are not enough to operate LEDs, relays, and other devices directly.
•The following figure illustrates a driver NAND gate that sources current when the output
is HIGH and sinks current when the output is low:

4/13/2012 ,V.V.Nagar. 19
 3.2 Fan In and Fan Out
 Fan In:
 The fan-in defined as the maximum number of inputs that a
logic gate can accept. If number of input exceeds, the output
will be undefined or incorrect.
 Fan Out:
 The fan-out is defined as the maximum number of inputs (load)
that can be connected to the output of a gate without degrading
the normal operation. Fan Out is calculated from the amount of
current available in the output of a gate and the amount of
current needed in each input of the connecting gate.

4/13/2012 ,V.V.Nagar. 20
 Fan Out:
.

4/13/2012 ,V.V.Nagar. 21
Fan Out:
 For example, Input and output currents for the transistor-transistor logic
(TTL) family are the following.
 Recall that negative current values indicate current flowing out of the
gate while positive current values indicate current flowing into the gate:
 IOH = -400 µA (i.e., output can source a maximum of 400µA)
 IOL = 16 µA (i.e., output can sink a maximum of 16µA)
 IIH = 40 µA (i.e., input can sink a maximum of 40µA)
 IIL = -1.6 µA (i.e., input can source a maximum of 1.6µA)
 Therefore the fan-out is min ( 400/40, 16/1.6) = min (10, 10) = 10.
 In other words, each TTL gate can drive 10 other TTL gates without
getting out of its guaranteed range of operation.
 If more than 10 gates were connected, the output voltage levels will degrade
and the gate will slow down.

4/13/2012 ,V.V.Nagar. 22
Fan Out:
•When the NOR gate output is HIGH, the output bin behaves as a current source since
IOH flows out of the driver gate and into the set of driven gates. The current IOH equals
the sum of all input currents indicated by IIH, flowing into the driven gates. In other
words, IOH = Sum of IIH.
•When the NOR gate output is LOW, the output bin behaves as a current sink since
IOL flows into the gate and out of the driven gates. The current IOL equals the sum of all
input currents indicated by IIL, flowing
Prof.Robinson
out of the driven gates. In other words,
Paul ,BVM Engineering College
I4/13/2012
OL = Sum of IIL. ,V.V.Nagar. 23
 3.3 Noise Margin:

4/13/2012 ,V.V.Nagar. 24
 Noise:
 Stray electric and magnetic fields can induce voltages on the
connecting wires between logic circuits,These unwanted, spurious
signals are called noise
 Noise Immunity:
 Circuit’s ability to tolerate noise without causing spurious changes
in the output voltage.
 Noise Margin:
 Quantitative measure of noise immunity is called Noise Margin.
 High-state noise margin : VNH = VOH (min) - VIH (min)
 Low-state noise margin : VNL = VIL (max) - VOL (max)
4/13/2012 ,V.V.Nagar. 25
 High-state noise margin : VNH = VOH (min) - VIH (min)

 Low-state noise margin : VNL = VIL (max) - VOL (max)
 Any noise voltage smaller than VOH - VIH will be tolerated and will not
change the output value of the driven gate.
 Any noise voltage smaller than VIL - VOL will be tolerated and will not
change the output value of the driven gate.
 For TTL:
 VNH = 2.7V - 2.0V = 0.7V.
 VNL = 0.8V - 0.5V = 0.3V.
 For CMOS:
 VNH = 4.95V - 3.5V = 1.45V.
 VNL = 1.5V - 0.05V = 1.45V.
 CMOS can tolerate much more noise than TTL.
4/13/2012 ,V.V.Nagar. 26
4/13/2012 ,V.V.Nagar. 27
LVC: Low Voltage CMOS.
LV: Low Voltage.
AVC: Advanced Very Low Voltage CMOS
CBT: Cross Bar Technology
TVC: Translation Voltage Clamp
4/13/2012 ,V.V.Nagar. 28
Propagation Delay
After an input to a logic gate changes, when does the output actually change?
V50% = (VOH + VOL) / 2.

tPHL: Difference in time between input and output signals for output to go
from HIGH to V50% (see tphl in diagram above)
tPLH: Difference in time between input and output signals for output to go
from LOW to V50% (see tplh in diagram above)
4/13/2012 ,V.V.Nagar. 29
Figure of Merit (Speed Power Product: SPP)
 A figure of merit of IC families is the product of their

propagation delay and power consumption, called the
speed-power product (SPP)
 the lower, the better.

4/13/2012 ,V.V.Nagar. 30
4/13/2012 ,V.V.Nagar. 31
Diode-Transistor Logic
 We can also use diodes in conjunction with transistors to
create Diode-Transistor Logic (or simply a DTL gate)
circuits. It is better to design a DTL gate than an RTL
gate because it is lot easier to create diodes than resistors
on a chip. A diode on the chip may in fact be a transistor
connected as a diode.

4/13/2012 ,V.V.Nagar. 32
4/13/2012 ,V.V.Nagar. 33
DTL NOR Gate:
 We can use a diode OR circuit and couple its output to a transistor
inverter (NOT) circuit in order to obtain a NOR gate. The resistance in
the base circuit RB is selected to limit the base current.

4/13/2012 ,V.V.Nagar. 34
DTL NOR Gate:

4/13/2012 ,V.V.Nagar. 35
4/13/2012 ,V.V.Nagar. 36
DTL NAND GATE
 We can use a diode AND circuit followed by a transistor
inverter (NOT) circuit to obtain a NAND gate.
•The minimum voltage at C to turn
on Q is 1.3 V [0.7 V for D3 and
0.6 V for Q].The maximum value
of the input voltage, VIL, for the
high output signal is 0.6 V [1.3 –
0.7].
•Thus, the lower-noise margin is
only 0.4 V. It would be better to
use at least one more diode in
series with D3 in order to increase
Prof.Robinson Paul ,BVMthe lower-noise
Engineering College margin.
4/13/2012 ,V.V.Nagar. 37
DTL NAND GATE

4/13/2012 ,V.V.Nagar. 38
4/13/2012 ,V.V.Nagar. 39
4/13/2012 ,V.V.Nagar. 40
4/13/2012 ,V.V.Nagar. 41
4/13/2012 ,V.V.Nagar. 42
4/13/2012 ,V.V.Nagar. 43
4/13/2012 ,V.V.Nagar. 44
4/13/2012 ,V.V.Nagar. 45
Prof.Robinson Paul ,
BVM Engineering College ,V.V.Nagar. 46
4/13/2012 ,V.V.Nagar. 47
4/13/2012 ,V.V.Nagar. 48
Reference:
 http://diranieh.com/Electrenicas/DigitalAnalog.htm
 University of Connecticut

4/13/2012 ,V.V.Nagar. 49

Chapter 6 Logic Families

Uploaded by

Copyright:

Available Formats

Chapter 6 Logic Families

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Chapter 6 Logic Families

Uploaded by

Copyright:

Available Formats

Prof.

Robinson Paul ,BVM Engineering College

(3) Describe the comparison of IC logic families.

(4) Explain with neat circuit diagram Tristate TTL devices.

Prof.Robinson Paul ,BVM Engineering College

1. Give the classification of Logic families. Also list the characteristics of

Prof.Robinson Paul ,BVM Engineering College

1. Define following parameters.

2. Give the comparison between various logic families.

Prof.Robinson Paul ,BVM Engineering College

Complexity Number of Gates

 (1) Saturated : RTL,DTL,DCTL,I2L,HTL,TTL

(B) Unipolar MOSFET transistors : NMOS, PMOS, and CMOS

Prof.Robinson Paul ,BVM Engineering College

Prof.Robinson Paul ,BVM Engineering College

Prof.Robinson Paul ,BVM Engineering College

 VOL (Voltage Output LOW):Maximum positive voltage

Prof.Robinson Paul ,BVM Engineering College

 3.3 Noise Margin:

Prof.Robinson Paul ,BVM Engineering College

Prof.Robinson Paul ,BVM Engineering College

Prof.Robinson Paul ,BVM Engineering College

Prof.Robinson Paul ,BVM Engineering College

Prof.Robinson Paul ,BVM Engineering College

The combination of Q3 and Q4 working as a push-pull transistor

Prof.Robinson Paul ,BVM Engineering College

Prof.Robinson Paul ,BVM Engineering College

Prof.Robinson Paul ,BVM Engineering College

Prof.Robinson Paul ,BVM Engineering College

 3.3 Noise Margin:

Prof.Robinson Paul ,BVM Engineering College

 High-state noise margin : VNH = VOH (min) - VIH (min)

V50% = (VOH + VOL) / 2.

 A figure of merit of IC families is the product of their

Prof.Robinson Paul ,BVM Engineering College

Prof.Robinson Paul ,BVM Engineering College

Prof.Robinson Paul ,BVM Engineering College

Prof.Robinson Paul ,BVM Engineering College

Prof.Robinson Paul ,BVM Engineering College

Prof.Robinson Paul ,BVM Engineering College

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.