Memory Hierarchy
Memory Hierarchy
Memory Hierarchy
Disk-based Storage
Oct. 23, 2008
Topics
Storage technologies and trends
Locality of reference
Caching in the memory hierarchy
lecture-17.ppt
Announcements
Exam next Thursday
style like exam #1: in class, open book/notes, no electronics
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Disk-based storage in
computers
Memory/storage hierarchy
Combining many technologies to balance
costs/benefits
Recall the memory hierarchy and virtual memory
lectures
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Memory/storage hierarchies
Balancing performance with cost
Small memories are fast but expensive
Large memories are slow but cheap
Exploit locality to get the best of both worlds
locality = re-use/nearness of accesses
allows most accesses to use small, fast memory
Capacity
Performance
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An Example Memory Hierarchy
Smaller, L0:
faster, registers CPU registers hold words
and retrieved from L1 cache.
costlier L1: on-chip L1
(per byte) cache (SRAM) L1 cache holds cache lines
retrieved from the L2 cache
storage memory.
devices L2: off-chip L2
cache (SRAM) L2 cache holds cache lines
retrieved from main memory.
5 From lecture-9.ppt
15-213, F’08
Page Faults
A page fault is caused by a reference to a VM word that
is not in physical (main) memory
Example: An instruction references a word contained in VP
3, a miss that triggers a page fault exception
Physical memory
Virtual address Physical page (DRAM)
number or
VP 1 PP 0
Vali disk address
VP 2
d 0
PTE 0 null VP 7
1 VP 4 PP 3
1
0
1
0 null Virtual memory
0 (disk)
PTE 7 1 VP 1
Memory resident VP 2
page table VP 3
(DRAM)
VP 4
VP 6
6 From lecture-14.ppt
VP 7 15-213, F’08
Disk-based storage in
computers
Memory/storage hierarchy
Combining many technologies to balance costs/benefits
Recall the memory hierarchy and virtual memory lectures
Persistence
Storing data for lengthy periods of time
DRAM/SRAM is “volatile”: contents lost if power lost
Disks are “non-volatile”: contents survive power outages
To be useful, it must also be possible to find it again later
this brings in many interesting data organization,
consistency, and management issues
take 18-746/15-746 Storage Systems
we’ll talk a bit about file systems next
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What’s Inside A Disk Drive?
Spindle
Arm Platters
Actuator
Electronics
SCSI
connector
Image courtesy of Seagate Technology
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Disk Electronics
Just like a small
computer – processor,
memory, network iface
• Connect to disk
• Control processor
• Cache memory
• Control ASIC
• Connect to motor
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Disk “Geometry”
Disks contain platters, each with two surfaces
Each surface organized in concentric rings called
tracks
Each track consists of sectors separated by gaps
tracks
surface
track k gaps
spindle
sectors
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Disk Geometry (Muliple-Platter
View)
Aligned tracks form a cylinder
cylinder k
surface 0
platter 0
surface 1
surface 2
platter 1
surface 3
surface 4
platter 2
surface 5
spindle
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Disk Structure
Upper Surface
Platter
Lower Surface
Cylinder
Track
Sector
Actuator
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Disk Operation (Single-Platter
View)
The disk
surface The read/write head
spins at a is attached to the end
fixed of the arm and flies over
rotational the disk surface on
rate a thin cushion of air
spindle
spindle
spindle
spindle
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Disk Operation (Multi-Platter
View)
read/write heads
move in unison
from cylinder to cylinder
arm
spindle
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Disk Structure - top view of
single platter
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Disk Access
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Disk Access
Rotation is counter-clockwise
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Disk Access – Read
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Disk Access – Read
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Disk Access – Read
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Disk Access – Seek
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Disk Access – Rotational
Latency
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Disk Access – Read
After BLUE read Seek for RED Rotational latency After RED read
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Disk Access – Service Time
Components
After BLUE read Seek for RED Rotational latency After RED read
Seek
Rotational Latency
Data Transfer
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Disk Access Time
Average time to access a specific sector approximated
by:
Taccess = Tavg seek + Tavg rotation + Tavg transfer
Seek time (Tavg seek)
Time to position heads over cylinder containing target sector
Typical Tavg seek = 3-5 ms
Rotational latency (Tavg rotation)
Time waiting for first bit of target sector to pass under r/w
head
Tavg rotation = 1/2 x 1/RPMs x 60 sec/1 min
e.g., 3ms for 10,000 RPM disk
25
given 512-byte sectors, ~85 MB/s data transfer rate 15-213, F’08
Disk Access Time Example
Given:
Rotational rate = 7,200 RPM
Average seek time = 5 ms
Avg # sectors/track = 1000
Derived average time to access random sector:
Tavg rotation = 1/2 x (60 secs/7200 RPM) x 1000 ms/sec = 4
ms
Tavg transfer = 60/7200 RPM x 1/400 secs/track x 1000 ms/sec
= 0.008 ms
Taccess = 5 ms + 4 ms + 0.008 ms = 9.008 ms
Time to second sector: 0.008 ms
Important points:
Access time dominated by seek time and rotational latency
First bit in a sector is the most expensive, the rest are free
SRAM access time is about 4 ns/doubleword, DRAM about 60
ns
~100,000 times longer to access a word on disk than in DRAM
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Disk storage as array of blocks
…5 6 7 12 23 …
OS’s view of storage device
(as exposed by SCSI or IDE/ATA protocols)
Common “logical block” size: 512 bytes
Number of blocks: device capacity / block size
Common OS-to-storage requests defined by few fields
R/W, block #, # of blocks, memory source/dest
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Page Faults
A page fault is caused by a reference to a VM word that
is not in physical (main) memory
“logical block”
Example: An instruction references number
a word can be
contained in VP
remembered
3, a miss that triggers a page in page table to
fault exception
Physical memory
Virtual address Physical identify
page disk location for pages
(DRAM)
number ornot resident in main memory
VP 1 PP 0
Vali disk address
VP 2
d 0
PTE 0 null VP 7
1 VP 4 PP 3
1
0
1
0 null Virtual memory
0 (disk)
PTE 7 1 VP 1
Memory resident VP 2
page table VP 3
(DRAM)
VP 4
VP 6
28 From lecture-14.ppt
VP 7 15-213, F’08
In device, “blocks” mapped to physical store
Disk Sector
(usually same size as block)
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Physical sectors of a single-
surface disk
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LBN-to-physical for a single-
surface disk
4 5
3 16 17
6
15 28 29 18
27 30
40 41
2 39 42 7
14 19
26
38 43 31
37 44 32
25
1 13 36 45 20 8
4 46
24 7 33
12 35 34 21
0 22 9
23
11 10
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Disk Capacity
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Computing Disk Capacity
Capacity = (# bytes/sector) x (avg. # sectors/track) x
(# tracks/surface) x (# surfaces/platter) x
(# platters/disk)
Example:
512 bytes/sector
1000 sectors/track (on average)
20,000 tracks/surface
2 surfaces/platter
5 platters/disk
ALU
main
bus interface
memory
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Connecting I/O devices: the I/O
Bus
CPU chip
register file
ALU
system bus memory bus
I/O main
bus interface
bridge memory
mousekeyboard monitor
disk
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Reading from disk (1)
CPU chip
CPU initiates a disk read by writing
register file
a READ command, logical block
number, number of blocks, and
ALU
destination memory address to a
port (address) associated with disk
controller
main
bus interface
memory
I/O bus
mousekeyboard monitor
disk
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Reading from disk (2)
CPU chip
Disk controller reads the sectors
register file
and performs a direct memory
access (DMA) transfer into main
ALU
memory
main
bus interface
memory
I/O bus
mousekeyboard monitor
disk
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Reading from disk (3)
CPU chip
When the DMA transfer
register file
completes, the disk controller
notifies the CPU with an
ALU
interrupt (i.e., asserts a special
“interrupt” pin on the CPU)
main
bus interface
memory
I/O bus
mousekeyboard monitor
disk
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