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    Md. Iftekharul Islam Sakib: Lecturer Cse, Buet

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    Md. Moniruzzaman
    (1) SAP-2 is an evolution of SAP-1 that includes jump instructions and bidirectional registers. (2) It uses a 16-bit program counter and memory address registers to access 64KB of RAM for program storage and execution. (3) The processor supports arithmetic, logic, and data transfer instructions through its accumulator, flags, temporary register, and ALU.

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    Md. Iftekharul Islam Sakib: Lecturer Cse, Buet

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    Md. Moniruzzaman
    230 views38 pages
    (1) SAP-2 is an evolution of SAP-1 that includes jump instructions and bidirectional registers. (2) It uses a 16-bit program counter and memory address registers to access 64KB of RAM for program storage and execution. (3) The processor supports arithmetic, logic, and data transfer instructions through its accumulator, flags, temporary register, and ALU.

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    SAP2

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    (1) SAP-2 is an evolution of SAP-1 that includes jump instructions and bidirectional registers. (2) It uses a 16-bit program counter and memory address registers to access 64KB of RAM for program storage and execution. (3) The processor supports arithmetic, logic, and data transfer instructions through its accumulator, flags, temporary register, and ALU.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    230 views38 pages

    Md. Iftekharul Islam Sakib: Lecturer Cse, Buet

    Uploaded by

    Md. Moniruzzaman
    (1) SAP-2 is an evolution of SAP-1 that includes jump instructions and bidirectional registers. (2) It uses a 16-bit program counter and memory address registers to access 64KB of RAM for program storage and execution. (3) The processor supports arithmetic, logic, and data transfer instructions through its accumulator, flags, temporary register, and ALU.

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    SAP-2

    Md. Iftekharul Islam Sakib


    Lecturer
    CSE, BUET
    Introduction
    • SAP-2 is the next step in the evaluation toward
    modern computers.
    • It includes jump instructions.
    Bidirectional Registers
    • Either enable or load only active .
    • During load input lines active output line float
    • During Enable output lines active input line
    float.

    • Input and output pins are shorted.


    • Single set of wires(path) between register and
    w-bus.
    Bidirectional Registers

    LOAD
    CLK
    Enable

    BUS
    Architecture
    Bus W
    Ack Encoder
    Hexa A
    8

    8
    In Port 1 8 8 ALU 2 Flag

    8
    Ready 0
    8
    Serial In
    7 In Port 2 8 TEMP

    PC 16
    8 B

    MAR 16 8 C
    16

    Memory
    8

    MDR 8 8 Out Port 3 8 Hexa Disp

    8 0
    IR 8 Out Port 4 7
    Serial Out
    Ack
    8

    CON
    Input port
    Port 1 and Port 2
    Port 1
    • Hexadecimal keyboard encoder
    • Sends ready signal to bit 0 of port 2 (indicates
    the data in port 1 is valid)
    Port 2
    Serial In
    Program Counter
    16 bit address

    Thus can count from


    PC= 0000 0000 0000 0000
    PC= 1111 1111 1111 1111(FFFFH)

    LOW CLR’
    MAR and MEMORY
    16- bit address to MAR (From 0000H  FFFFH)
    0000 H
    ROM
    07FF H
    0800 H

    • MAR OUTPUT to RAM RAM

    • Memory Capacity(?????) FFFF H

    • 2K ROM(0000H-07FFH) => Monitor Program


    • 62K RAM(0800H-FFFFH)
    Memory Data Register
    • 8-bit Register
    • Output setup RAM
    • Receives data from the bus before write
    operation
    • Data to the bus after read operation
    Instruction Register
    • 8-bit op code
    • Can accommodate 256 instruction
    • Only 42 instruction
    Controller Sequencer
    As usual
    • Generates the control words
    (microinstructions)
    • Has more hardware(larger number of
    instruction)
    • Control Word is bigger (CON)
    Accumulator

    Same as SAP-1
    ALU and Flags
    • ALU: Includes both arithmetic and logical
    operation
    • 4 or more control bits for determining the
    operation to be performed

    • Flag: Represent the status of the arithmetic and


    logical operation
    • Filp flops are used;
    • Zero Flag(Z)
    • Sign Flag(S)
    Temp, B and C registers
    • Temporary register (TEMP)
    • Register B and C are used to move data during
    program run and accessible to programmers.
    Output Ports
    2 output ports(3 and 4)

    • Port 3 : Drives Hexadecimal display

    • Port 4: sends ACKNOWLEDGE signals used to


    hexadecimal encoder. (Handshaking)
    Serial Out: Serial Transmission of data.
    Microprocessor Instruction
    LDA and STA

    Eg:
    LDA 2000H
    STA 8000H
    MVI
    MVI-Move Immediate

    MVI A,37H

    MVI A,byte
    MVI B,byte
    MVI c, byte
    Register Instruction
    MOV

    MOV A,B
    MOV A,C
    MOV B,A
    MOV B,C
    MOV C,A
    MOV C,B
    Register Instruction
    ADD and SUB

    Eg ADD B /SUB B

    ADD B
    ADD C
    SUB B
    SUB C
    Register Instruction
    INR and DCR

    INR A/DCR A
    INR B/DCR B
    INR C/DCR C
    Jump And Call Instruction
    JMP

    JMP 3000H

    JM (Jump if Minus)
    JZ(Jump if zero)
    JNZ(Jump if not zero)
    Jump And Call Instruction
    CALL
    Subroutine ????

    Call is used to call the subroutine


    Ret
    Return back from subroutine
    Program Counter contents ????
    -----stored in the last two location of memory
    (FFFEH and FFFFH)
    Logic Instruction
    CMA-Complement the accumulator
    ANA-And the accumulator with specified register
    eg ANA B
    ORA- OR the accumulator with specified register
    eg ORA B
    XRA- XOR the accumulator with specified register
    eg XRA B
    Logic Instruction Contd.
    ANI: And Immediate

    Eg ANI C7H (AND accumulator with immediate


    data C7H)
    ORI: OR immediate
    Eg ORI C7H
    XRI: XOR immediate
    Eg XRI C7H
    Other Instruction
    • OUT (OUT byte eg: OUT 03H: accumulator to designated port)
    • HLT
    • IN (Input : Enter the data from designated input port to
    accumulator) eg: IN 02H
    • NOP
    • RAL(Rotate the accumulator left)
    A=1011 0100 After execution
    A=0110 1001
    • RAR (Rotate the accumulator right)
    A= 1011 0100
    After execution
    A=0101 1010
    SAP-2 Op codes
    Instruction Affecting Flags
    T-States

    • Fetch  3 T-States
    • Execution  Different instruction requires
    different # of T-States
    • Ex: ADD B  4
    • ANI byte  7
    • CALL  18
    • JM  10/7
    Summary 1
    Summary 2
    Handshaking
    Handshaking
    Math-1
    Math-1
    Solution of Math-1
    Math-2
    Solution of Math-2
    Thank you

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