Definition:

• Counter : A sequential circuit that goes through prescribed

sequence of states upon the application of clock pulse is
called a counter.
• The input pulses are called count pulses, may be clock pulses
or they may originate from an external source or occur at
prescribed intervals or at random.
• In a counter the sequence of states may follow binary count
or any other sequence.
• Counters are found in almost all equipment containing
digital system
 Binary Counter :

• Binary Counter : A counter that follows the

binary
• sequence is called
An n-bit Binary a Binary
Counter counter.
consists of n flipflops and
can count in binary from 0 to 2n-1.
• For eg. Binary counter for two digits is as follows:
1
Present Next 00 01
State State
A
0 B
0 A
0 B1
1 1
0 1 1 0
1 0 1 1 1
1 1 0 0 11 10
 Example of binary counter
• Here’s the another example for binary counter and its state
table:

Present State Inputs Next State

0 Q1 Q0 X Q1 Q0
00 01 0 0 0 0 1
1 0 0 1 1 1
0 1 1 0
0 1 0 1 0
0 1 1 0 0
1 1 0 0 1 1
11 10 1 0 1 0 1
0 1 1 0 0 0
1 1 1 1 0
 Applications of Counters
• Some of the applications of counters in a
sequential circuits are as follows:
 To count the number of occurances
 Generating Timing sequences
 Count up or down
 Increment or decrement count
 Sequence events
 Divide frequency
 Address memory
 As temporary memory
 Two principal categories

• Counters are divided in two categories,

these
are:
– Asynchronous (Ripple) Counters - the first flip-flop
is clocked by the external clock pulse, and then
each successive flip-flop is clocked by the Q or Q'
output of the previous flip-flop.
– Synchronous Counters - all memory elements are
simultaneously triggered by the same clock.
 Few other categories of counters:

• Apart from synchronous and asynchronous

counters which are the major ones the other
types of counters are as follows:
– Ring counter
– Johnson counter
– Decade counter
– Up–down counter
 Asynchronous Counters:

• Here flipflop output transition serves as a source for

triggering other flipflops.
• This means that that the clockpulse is provided to a
single flipflop
• The change of state of a given flipflop is dependent
on the states of other flipflops.
• In other words the flipflops are not triggered by
simultanous clock pulses but the transitions in
other flipflops.
 Asynchronous Counters
• This counter is called
asynchronous because not all flip
flops are have the same clock.
• Look at the waveform of the
output, Q, in the timing diagram.
It resembles a clock as well.
• This provides a clock that runs
twice as slow. If we feed the
clock into a T flip flop, where T is
hardwired to 1. The output will
be a clock who's period is twice
as long.
 Two-bit asynchronous counter
• The external clock is
connected to the clock
input of the first flip-flop
only.
• So, it changes state at the
negative edge of each
clock pulse, but the next
flipflop changes only
when triggered by the
negative edge of the Q
output of the first one.
 Two-bit asynchronous counter
• Because of the inherent
propagation delay through a
flip-flop, the transition of
the input clock pulse and a
transition of the Q output of
FF0 can never occur at
•
exactly the same time.
Therefore, the flip-flops
cannot be triggered
• simultaneously, producing
an asynchronous operation.
Eg : As shown, there is some
small delay between the
CLK, Q0 and Q1 transitions.
 Two-bit asynchronous counter
• Usually, all the CLEAR inputs are connected
together,
so that a single pulse can clear all the flip-flops
• before counting starts.
The 2-bit ripple counter circuit above has four
different states, each one corresponding to a count
• value.
Similarly, a counter with n flip-flops can have 2N
states.
• The number of states in a counter is known as its
mod (modulo) number.
 Two-bit asynchronous counter

• Thus a 2-bit counter is a .

mod-4 counter.

• This is because the

most significant flip-flop
produces one pulse for
every n pulses at the
clock input of the least
significant flip-flop .
 3 bit asynchronous “ripple” counter
using T flip flops
• Thisis called as a ripple
counter due to the way the
FFs respond one after
another in a kind of
rippling effect.
 Synchronous Counters
• To eliminate the "ripple" effects, use a common clock for
each flip-
• flop and a combinational circuit to generate the next state.
For an
use anincrementer
up-counter,=>

Incre-
menter
A3 S3 D3 Q3
A2 S2 D2 Q2
A1 S1 D1 Q1
A0 S0 D0 Q0

Clock
 Synchronous Counters

• To eliminate the "ripple" effects, use a clock

common for each flip-flop and a combinational
circuit to generate the next state.
• Hence the counters in which all the flipflops are
provided with a clock pulse simultanously are called
the Synchronous counters.
• Synchronous counters may be of the following types
– Up counter
– Down counter
Synchronous Counters (continued)
• Internal details =>In crementer

• Internal Logic
– XOR complements each bit
– AND chain causes omplement
c ward LSB
of a bit if all bits to
•
from it equal 1
of AND
Count Enable ” the state
• –chain
Forces all outputs
to 0 to “hold
Carry Out ncrementer
– Added as part of i
nable of
unters to
– Connect to Count rs
additional 4-bit co
form larger counte
Design Example: Synchronous BCD
• Use the sequential logic model to design a synchronous BCD counter with
D flip-flops
• State Table =>
• Input combinations Current State Next State
1010 through 1111 Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1
are don’t cares
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 0 0 0 0
 Synchronous BCD (continued)
• Use K-Maps to two-level optimize the next state
equations and manipulate into forms containing XOR
gates:
D1 = Q1’

• D2 = Q2 + Q1Q8’
D4 = Q4 + Q1Q2
D8 = Q8 + (Q1Q8 + Q1Q2Q4)
• Y = Q1Q8

• The logic diagram can be drawn from these equations

– An asynchronous or synchronous reset should be added
 Synchronous BCD (continued)
• There are chances that . Present State Next State

counter is perturbed by a Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1

power disturbance or other

1 0 1 0 1 0 1 1
interference and it enters a
state other than 0000 1 0 1 1 0 1 1 0
• through 1001.
1 1 0 0 1 1 0 1
Find the actual values of
the 1 1 0 1 0 1 0 0

• six next states for the don’t 1 1 1 0 1 1 1 1

care combinations from the
1 1 1 1 0 0 1 0
equations
Find the overall state
diagram to assess behavior
for the don’t care states
 Unused states
• The examples shown so . Present State Next State
far have all had 2n states, Q2 Q1 Q0 Q2 Q1 Q0
and used n flip-flops. But 0 0 0 0 0 1
0 0 1 0 1 0
sometimes you may have 0 1 0 0 1 1
unused, leftover states. 0 1 1 1 0 0
• 1 0 0 1 0 1
For example, here is a 1 0 1 0 0 0
1 1 0 ? ? ?
state table and diagram 1 1 1 ? ? ?
repeatedly counts
for a counter thatfrom 0
(000) to 5 (101).
000
• But there are also the 101 001
unused states in the state
table. 100 010
011
Unused states can be don’t cares…
Present State Next State
• To get the simplest possible . Q2 Q1 Q0 Q2 Q1 Q0
circuit, one can fill in don’t 0 0 0 0 0 1
cares for the next states. 0 0 1 0 1 0
This will also result in don’t 0 1 0 0 1 1
0 1 1 1 0 0
cares for the flip-flop inputs,
1 0 0 1 0 1
which can simplify the 1 0 1 0 0 0
hardware. 1 1 0 x x x
• If the circuit somehow ends 1 1 1 x x x

up in one of the unused 000

states (110 or 111), its 101 001
behavior will depend on
exactly what the don’t cares 100 010
were filled in with. 011
 Other possibility
• To get the safest possible . Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0

circuit, you can explicitly 0 0 0 0 0 1

0 0 1 0 1 0
fill in next states for the 0 1 0 0 1 1
0 1 1 1 0 0
unused states 110 and 1 0 0 1 0 1
• 111. 1 0 1 0 0 0
1 1 0 0 0 0
This guarantees that even 1 1 1 0 0 0

if the circuit somehow 110 111

enters an unused state, it
000
• will eventually end up in a
101 001
valid state.
This is called a self-
starting counter. 100 010

011
Ring Counter

Ring counters are implemented as shown where output of a flipflop is

given as an input to the next flipflop except the last one. Here the
normal output of the last flipflop is connected back to the input of
the
first one. Hence it is called Ring counter.
Johnson Counter

The Johnson counter, also known as the twisted-ring counter,

is exactly the same as the ring counter except that the inverted
output of the last flip-flop is connected to the input of the first
flip-flop.
If it starts from 000, 100, 110, 111, 011 and 001, and
the sequence is repeated so long as there is input pulse.
Modulus (MOD) – the
number of states it counts
before it goes back to the initial state.
in a complete cycle
Thus, the number of flip-flops used depends on the MOD of the counter
(ie; MOD-4 use 2 FF (2-bit), MOD-8 use 3 FF (3-bit), etc..)
Example: MOD-4 Ripple/Asynchronous Up-Counter.