80x86

80186
• Intel 80186 is a microprocessor and
microcontroller introduced in 1982.
• It was based on the Intel 8086,
• & like it, had a 16-bit external data bus
multiplexed with a 20-bit address bus.
• 68 pins
• 29,000 transistors

• ~ as an embedded version of 8086.

• Added 7 new instructions: push all, pop all,
etc.
• 1982 ~ Sept. 2007.
 80286 / iAPX 286
• February 1, 1982
• Bus Width: 16 bits data, 24 bits address.
• Included memory protection hardware to
support multitasking operating systems with
per-process address space
• Number of Transistors 134,000
• Addressable memory 16 MB
• 3~6X the performance of the 8086
• 4 independent units:
– address unit,
– bus unit,
– instruction unit and
– execution unit,

which formed a pipeline significantly increasing the performance.

In computing, a pipeline is a set of data processing elements connected in
series, so that the output of one element is the input of the next one.
The elements of a pipeline are often executed in parallel or in time-sliced
fashion; in that case, some amount of buffer storage is often inserted
between elements.
 386DX
• Introduced October 17, 1985
• Bus Width 32 bits data, 32 bits address
• Number of Transistors 275,000
• Addressable memory 4 GB
• Virtual Memory – 64 TB
• First x86 chip to handle 32-bit data sets

• Used in desktop computing

 …386SX
• June 16, 1988

• a low cost version of the 80386 with a 16-bit data

bus.

• The original 80386 was subsequently renamed

i386DX to avoid confusion.
• However, Intel subsequently used the 'DX' suffix to
refer to the floating-point capability of the i486DX.
 …386EX
• Introduced August 1994
• Variant of 80386SX intended for embedded systems
• Static core, i.e., may run as slowly (and thus, power
efficiently) as desired, down to full halt
– Static core is a CPU chip that can be stopped simply by
stopping the system clock oscillator that is driving it, and it
will hold its state indefinitely and resume processing at the
point it was stopped when the clock signal is restarted, as
long as it is kept powered.
– It allows the use of less power, and is suitable for standby
mode.
• On-chip peripherals:
– Clock and power management
– Timers/counters
– Watchdog timer
– Serial I/O units (sync and async) and parallel I/O
– DMA
– RAM refresh

• Used aboard several orbiting satellites and microsatellites

• Used in NASA's FlightLinux project
 Watchdog – regulator - supervisory body
• A watchdog timer (or computer operating properly
(COP) timer) is a computer hardware or software timer 
that triggers a system reset or other corrective action,
if the main program [due to some fault condition, e.g.,
a hang] neglects to regularly service the watchdog by writing
a "service pulse" to it (aka, "kicking the dog", “petting the
dog”, "feeding the watchdog“ or "waking the watchdog").

The intention is to bring the system back:

from an unresponsive state  into normal operation.
 DMA
• Direct memory access (DMA) is a feature of
modern computers that allows certain hardware subsystems
within the computer to access system memory independently
of the CPU!
• Without DMA, when the CPU is using programmed
input/output, it is typically fully occupied for the entire duration
of the read or write operation, and is thus unavailable to
perform other work.
• With DMA, the CPU initiates the transfer, does other operations
while the transfer is in progress, and receives an interrupt from
the DMA controller when the operation is done.
• This feature is useful any time the CPU cannot keep up with the rate
of data transfer, or where the CPU needs to perform useful work
while waiting for a relatively slow I/O data transfer.
• Many hardware systems use DMA, including disk
drive controllers, graphics cards, network cards and sound cards.
• DMA is also used for intra-chip data transfer in multi-core
processors.
• Computers that have DMA channels can transfer data to and from
devices with much less CPU overhead than computers without a
DMA channel.
• Similarly, a processing element inside a multi-core processor can
transfer data to and from its local memory without occupying its
processor time, allowing computation and data transfer to proceed
in parallel.
 i386SL
• The i386SL was introduced as a power efficient version
for laptop computers.
• The processor offered several power management
options (e.g., SMM – System Management Mode), as well
as different "sleep" modes to conserve battery power.
• It also contained support for an external cache of 16 to
64 kB.
• The extra functions and circuit implementation
techniques caused this variant to have over 3 times as
many transistors as the i386DX.
 SMM
• The system management mode - is an operating
mode in which all normal execution (including
the operating system) is suspended, and special
separate software (usually firmware or a
hardware-assisted debugger) is executed in
high-privilege mode.
• It is intended for use only by system firmware,
not by applications software or general-purpose
systems software.
• The first company to design and manufacture
a PC based on the Intel 80386 was Compaq –
the 1st 3rd-party to implement a major
technical hardware advance on the PC
platform. 

• The 80486 and P5 Pentium line of processors
were descendants of the 80386 design.
32-bit processors: the 80486 range
 ..486DX
• April ‘89
• Bus width – 32 bits
• No. of transistors – 1.2 million
• Addressable memory 4 GB
• Virtual memory 1 TB
• Level 1 cache of 8 KB on chip
• Math coprocessor on chip
• 50X performance of the 8088
• Used in Desktop computing and servers
 ..486SX
• April ‘91
• Identical in design to 486DX but without math
coprocessor.

• Used in low-cost entry to 486 CPU desktop

computing, as well as extensively used in low
cost mobile computing.
 32-bit processors: 
P5 micro-architecture
 Pentium
• Bus width 64 bits
• Address bus 32 bits
• Addressable Memory 4 GB
• Virtual Memory 64 TB

• Superscalar architecture
• Used in desktops
• 8 KB of instruction cache
• 8 KB of data cache
• P5
– Mar ‘93
– 3.1 mil transistors

• P54
– 3.2 mil tran.
 Pentium with MMX tech.
• Jan. ‘97
• Intel MMX (instruction set) support
• 16 KB L1 instruction cache
• 16 KB L1 data cache
• Number of transistors 4.5 million
• System bus clock rate 66 MHz
• Variants –
– 166, 200 MHz Introduced January 8, 1997
– 233 MHz Introduced June 2, 1997
– 133 MHz (Mobile)
– 166, 266 MHz (Mobile) Introduced January 12, 1998
– 200, 233 MHz (Mobile) Introduced September 8, 1997
– 300 MHz (Mobile) Introduced January 7, 1999
 32-bit processors: 
P6/Pentium M microarchitecture
 Pentium Pro
• Nov. ‘95
• Precursor to Pentium II and III
• Primarily used in server systems
• 5.5 mil trans.

• 16 KB L1 cache
• 256 KB integrated L2 cache
• 60 MHz system bus clock rate
 Pentium II
• May 7, 1997
• Pentium Pro with MMX and improved 16-bit
performance
• 242-pin processor package
• Number of transistors 7.5 million
• 32 KB L1 cache
• 512 KB ½ bandwidth external L2 cache
• The only Pentium II that did not have the L2 cache at ½ bandwidth of
the core was the Pentium II 450 PE.
 Celeron [Pentium II-based]
• Introduced April 15, 1998
• 242-pin SEPP (Single Edge Processor Package)
• Number of transistors 7.5 million
• 66 MHz system bus clock rate

• 32 KB L1 cache
• No L2 cache
• Variants
– 266 MHz Introduced April 15, 1998
– 300 MHz Introduced June 9, 1998
 Pentium III
• Feb. ‘99
• Improved PII, i.e., P6-based core, now
including Streaming SIMD Extensions (SSE)
• Number of transistors 9.5 million
• 512 KB ½ bandwidth L2 External cache
• 242-pin SECC2 (Single Edge Contact cartridge 2)
processor package
• System Bus clock rate 100 MHz, 133 MHz (B-
models)
Celeron (Pentium III Coppermine-based)

• Mar. 2000
• 28.1 mil trans.

• 66 MHz system bus clock rate, 100 MHz

system bus clock rate from January 3, 2001
• 32 kB L1 cache
• 128 kB Advanced Transfer L2 cache
 Pentium 4
• Introduced April 2000 – July 2002
 Celeron (Pentium III Tualatin-based)
• 32 KB L1 cache
• 256 KB Advanced Transfer L2 cache
• 100 MHz system bus clock rate
• Family 6 model 11
• Variants
– 1.0 GHz
– 1.1 GHz
– 1.2 GHz
– 1.3 GHz
– 1.4 GHz
 Pentium M
• Mar. 2003
• 64 KB L1 cache
• 1 MB L2 cache (integrated)
• Based on Pentium III core, with SSE2 SIMD
instructions and deeper pipeline
• Number of transistors 77 million
• Heart of the Intel mobile Centrino system
• Variants –
– 900 MHz (ultra low voltage)
– 1.0 GHz (ultra low voltage)
– 1.1 GHz (low voltage)
– 1.2 GHz (low voltage)
– 1.3 GHz
– 1.4 GHz
– 1.5 GHz
– 1.6 GHz
– 1.7 GHz …
– 2.1 GHz
 Celeron M
• Mar. 2003

• 64 KB L1 cache
• 512 KB L2 cache (integrated)
• SSE2 SIMD instructions
• No SpeedStep technology, is not part of the
'Centrino’ package
 Intel Core
• Jan. 2006

• Intel Core Duo T2700 2.33 GHz

• Intel Core Duo T2600 2.16 GHz
• Intel Core Duo T2500 2 GHz
• Intel Core Duo T2450 2 GHz
• Intel Core Duo T2400 1.83 GHz
• Intel Core Duo T2300 1.66 GHz
• Intel Core Duo T2050 1.6 GHz
• Intel Core Duo T2300e 1.66 GHz
• Intel Core Duo T2080 1.73 GHz
• Intel Core Duo L2500 1.83 GHz (low voltage, 15W TDP)
• Intel Core Duo L2400 1.66 GHz (low voltage, 15W TDP)
• Intel Core Duo L2300 1.5 GHz (low voltage, 15W TDP)
• Intel Core Duo U2500 1.2 GHz (ultra low voltage, 9W TDP)
• Intel Core Solo T1350 1.86 GHz (533 FSB)
• Intel Core Solo T1300 1.66 GHz
• Intel Core Solo T1200 1.5 GHz