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Computer Architecture Taxonomy

This document discusses four main computer architecture styles: Von Neumann, Harvard, CISC, and RISC. It provides details on the characteristics of each style, including their memory models, instruction sets, advantages, and disadvantages. ARM processors are then discussed as an example of RISC architecture, describing their operating states, memory organization, and basic data operations via load and store instructions.

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Suresh Varuvel
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86 views

Computer Architecture Taxonomy

This document discusses four main computer architecture styles: Von Neumann, Harvard, CISC, and RISC. It provides details on the characteristics of each style, including their memory models, instruction sets, advantages, and disadvantages. ARM processors are then discussed as an example of RISC architecture, describing their operating states, memory organization, and basic data operations via load and store instructions.

Uploaded by

Suresh Varuvel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Computer architecture taxonomy

Four different kinds of architecture styles


• Von Neumann Architecture
• Harvard Architecture
• Complex instruction set computers (CISC)
• Reduced instruction set computers (RISC).
Von Neumann Architecture
• John Von Neumann suggested that data and programs should
be stored together in memory.
• main criticism - security problems

• PC hold the memory address


Harvard Architecture

• Separate memory for data and program


• PC points Program memory
Complex instruction set computers (CISC)
• It uses Von Neumann Architecture
• Same bus for program memory, data memory, I/O, registers etc
Features:
• CISC supports microprogramming.
• CISC have more number of predefined instructions which makes
high level languages easy to design and implement.
• CISC consists of less number of registers and more number of
addressing modes, generally 5 to 20.
• Because of the complex instruction set of the CISC, the
pipelining technique is very difficult.
• CISC consists of more number of instructions, generally from 100
to 250.
• Special instructions are used very rarely.
Complex instruction set computers (CISC)

Advantages of CISC architecture


• Each machine language instruction is grouped into a microcode
instruction and executed accordingly, and then are stored inbuilt in the
memory of the main processor, termed as microcode implementation.
• As the microcode memory is faster than the main memory
• Entire new instruction set can be handled by modifying the micro
program design.
Drawbacks of CISC
• The amount of clock time taken by different instructions will be
different – due to this – the performance of the machine slows down.
• Only 20% of the existing instructions are used in a typical programming
event, even though there are many specialized instructions in existence
which are not even used frequently.
Reduced instruction set computers (RISC).

Features
• One Cycle Execution.
• It optimizes the usage of register
• Simple addressing modes, even complex addressing can
be done by using arithmetic AND/OR logical operation.
• It simplifies the compiler design
• For efficient usage of the registers and optimization of
the pipelining uses, reduced instruction set is required.
• The number of bits used for the Opcode is reduced.
• In general there are 32 or more registers in the RISC.
Reduced instruction set computers (RISC).

Advantages
• Because of the small set of instructions of RISC, high-level language compilers can
produce more efficient code.
• RISC allows freedom of using the space on microprocessors because of its simplicity.
• Instead of using Stack, many RISC processors use the registers for passing arguments and
holding the local variables.
• RISC functions uses only a few parameters, and the RISC processors cannot use the call
instructions, and therefore, use a fixed length instructions which are easy to pipeline.
• The speed of the operation can be maximized and the execution time can be minimized.
• Very less number of instruction formats (less than four), a few number of instructions
(around 150) and a few addressing modes (less than four) are needed.
Drawbacks of RISC processor architecture
• With the increase in length of the instructions, the complexity increases for the RISC
processors to execute due to its character cycle per instruction.
• The performance of the RISC processors depends mostly on the compiler or programmer
as the knowledge of the compiler plays a major role while converting the CISC code to a
RISC code; hence, the quality of the generated code depends on the compiler.
Instruction characteristic

What is an instruction set?


• The complete collection of instructions that are understood by a CPU
• Machine Code
• Binary
• Usually represented by assembly codes
Instruction set defines the interface between software module and
underlying hardware
Instruction characteristic
• Fixed Vs Variable length
• Addressing modes
• Numbers of operands
• Types of operations supported
Programming model or programmer model
• Set of registers available for the programs not for programmer
Assembly language
• Assembly language is a low-level programming
language
• Instructions are expressed using mnemonics
• e.g. the word “ADD”
Assembly language must still be translated into machine code
• Done using a program called an assembler
• Machine code produced by the assembler is
stored in memory and executed by the
processor
ARM 7 Processor and Memory Organization
• Advanced RISC Machine
• ARM7- von Neumann Architecture
• ARM9 –Harvard Architecture
ARM7TDMI processor features
• A 32-bit RISC engine,
• Thumb instruction set (smaller code size),
• Debug functions
• Multiplier
• Embedded ICE support logic.
Processor Operating States
The ARM7TDMI processor has two operating states:
– ARM - 32-bit, word-aligned ARM instructions are executed in this state.
– Thumb -16-bit, half word-aligned Thumb instructions are executed in
this state.
ARM 7 Processor and Memory Organization
Memory endianness
• The processor views memory as a linear collection of bytes numbered in ascending order from zero.
• For example,
– bytes 0-3 hold the first stored word,
– bytes 4-7 hold the second stored word.
possible implementations:
• Big-endian format
• Little-endian format
Big-endian format
• In byte-invariant big-endian format, the processor stores the most significant byte of a
word at the lowest-numbered byte, and the least significant byte at the highest-
numbered byte.
Little-endian format
• In little-endian format, the processor stores the least significant byte of a word at the
lowest-numbered byte, and the most significant byte at the highest-numbered byte.
Data operation
The ARM is a Load / Store Architecture:
– Does not support memory to memory data processing operations.
– Must move data values into registers before using them.
– Load data values from memory into registers.
– Process data in registers using a number of data processing instructions which are not
slowed down by memory access.
– Store results from registers out to memory.
The ARM has three sets of instructions which interact with main memory. These are:
– Single register data transfer (LDR / STR).
– Block data transfer (LDM/STM).
– Single Data Swap (SWP).
The basic load and store instructions are:
– Load and Store Word or Byte
• LDR / STR / LDRB / STRB
ARM Architecture Version 4 also adds support for halfwords and signed data.
– Load and Store Halfword
• LDRH / STRH
– Load Signed Byte or Halfword - load value and sign extend it to 32 bits.
• LDRSB / LDRSH

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