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St. Joseph College of Engineering

The document discusses the hardware architecture of the 8085 processor, including its register structure. It describes the different types of registers in the 8085 like general purpose registers, temporary registers, special purpose registers and stack pointer. It provides details about each register and its purpose.

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30 views

St. Joseph College of Engineering

The document discusses the hardware architecture of the 8085 processor, including its register structure. It describes the different types of registers in the 8085 like general purpose registers, temporary registers, special purpose registers and stack pointer. It provides details about each register and its purpose.

Uploaded by

jaisathi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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ST.

JOSEPH COLLEGE OF ENGINEERING


DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

1
EE8551 - MICROPROCESSORS AND
MICROCONTROLLERS

LECTURE – 1
13.08.2020

Presented by
J.Jayashree AP/EEE
SJCE
UNIT – 1 8085 PROCESSOR
Hardware Architecture
Register Structure:
The registers of 8085 are classified as :
1. General Purpose Registers
2. Temporary Registers
(i) Temporary Data Register (ii) W and Z Register
3. Special Purpose Registers
(i) Accumulator (ii) Flag Registers (iii) Instruction Register
4. Sixteen Registers
(i) Program Counter (PC) b. Stack Pointer
General Purpose Registers :
B, C, D, E, H and L are 8- bit general purpose registers and can be used
as a separate 8 – bit registers or as 16-bit register pairs , BC, DE
and HL.
UNIT – 1 8085 PROCESSOR
Hardware Architecture
Register Structure:
General Purpose Registers :
• When used as register pairs (BC , DE and HL) the higher order byte
resides in the first register and the Lower order pair resides in the
second register.
• HL has another function – it acts as a memory pointer or a data
pointer.
• The General Purpose registers are otherwise called scratch pad
registers.
• The bus access is not required for these operations, it is an internal
operation.
• The immediate results can be stored in these registers.
UNIT – 1 8085 PROCESSOR
Hardware Architecture
Register Structure:
Temporary Registers:
Temporary data register:
The ALU ( Arithmetic and Logic Unit) has two inputs
 One from the Accumulator
 Other from the temporary date register.
The temporary data register is not accessible to the programmer. It is used internally for the
arithmetic and logic operations.
Example : ADD B is an instruction.
 The first content is from the accumulator A.
 The second content is from the Register B.
 The addition operation is performed in the ALU , and the results are stored in the accumulator A.
 The contents of the register, B is transferred to the temporary internal register for addition.
W and Z registers :
 W and Z registers are temporary registers.
 These registers are used to store the 8-bit data during execution of some instructions.
 These are used by the 8085 internally.
UNIT – 1 8085 PROCESSOR
Hardware Architecture
Register Structure:
Special Purpose Registers:
Register A (Accumulator) :
 It is a tri-state 8 – bit register.
 It is used in arithmetic, logic, load and store operations as well as in I/O
operations.
 Most of the times the results of the arithmetic operations are stored in the
register A. Hence, it is identified as the Accumulator.
Flag Register : It is an eight bit register.
It has five bits, which carry significant information in the form of bits.
S – Sign Flag
Z – Zero Flag
AC – Auxillary Carry Flag
P- Parity Flag
CY – Carry Flag
UNIT – 1 8085 PROCESSOR
Hardware Architecture
Register Structure:

S – Sign Flag:
After the execution of arithmetic and logical operations, if bit D7 of the
result is 1, the S – flag is set to 1, otherwise it is set to 0. If D7 is 0
(Zero) then it is considered to be a positive number.
Z- Zero Flag :
The Zero flag is set , if the result of a operation is zero, otherwise it is reset
AC – Auxillary Carry Flag:
The flag is set, if there is an overflow out of bit 3, carry from lower nibble
to higher nibble (D3 to D4 bit) . This flag is used for BCD operations.
UNIT – 1 8085 PROCESSOR
Hardware Architecture
Register Structure:
P – Parity Flag
Parity is defined by the number of ones present In the accumulator.
After an arithmetic or logical operation, if the result of the operation
has even number of ones, i.e., even parity., the flag is set. If the
parity is odd. Flag is reset.
CY – Carry Flag:
This flag is set if there is an overflow out of bit 7. The carry flag also
serves as a borrow flag for subtraction.
THANK YOU
9

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