Department of Electrical and Computer Engineering

SystemVerilog and
Verification
Cody Rigby
 Department of Electrical and Computer Engineering

Topics
 What is SystemVerilog
 Differences from VHDL
 Features

 Constructing a Basic Testbench Topology in SystemVerilog

 Modules
 UVM SystemVerilog

 Verification Concepts
 Assertions
 Coverage
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SystemVerilog
 Hardware Description and Verification Language (HDVL) combines features of HDL’s with features from C and C++
 Borrows features from Verilog Superlog, VHDL, PSL, C, Vera,
 Most of the verification functionality is based on the OpenVera language by Synopsys
 Adopted as IEEE standard in 2005, most current version is IEEE standard 1800-2017
 Can be used to describe hardware behavior but typically used for verification
 SystemVerilog is an Object Oriented language that supports a single-inheritance model
 Verification features allow for complex testbenching and random stimuli in simulation
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SystemVerilog VHDL
 C-style data types 7 control –enum, struct, typedef, ++ break return Yes
 Packages Yes
RTL  Synthesis –friendly “concise” RTL notation No
 Interfaces No
Assertions  Systemverilog Assertions Yes
 Clocking Blocks No
 Object Oriented Programming –Classes No
Test Bench  Constrained random stimulus generation No
 Function Coverage No
 Dynamic Processes, Dynamic arrays, queues, mailboxes, semaphores No
DPI  Direct Programming Interface(DPI) –calling C from Systemverilog Yes
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SystemVerilog Types
 wire : acts like real write in circuits
 reg : holds values until another value is assigned, like register in hardware
 real, shortreal : single and double precision floating point numbers
 Time : 64 bit quantity used to hold simulation time
 Logic : improved version of reg from Verilog to SystemVerilog, can be driven by continuous
assignments, gates and modules in addition to being a variable
 Two State Types : byte, bit, int, shortint, longint : improved performance and memory usage
 event : event is a handle to a synchronization object that can be passed around to routines,
SystemVerilog introduces triggered function that lets you check whether an event has been
triggered
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SystemVerilog Data Structures

 Fixed Arrays : collection of variables all the same type
 bit [7:0] array4 [2:0];        //unpacked array declaration
 bit [2:0][7:0] array5;         //packed array declaration

 Vector width/dimensions declared before the object name referenced as packed array, array size/dimensions declared
after object name is refereed as unpacked array

 Dynamic Arrays : one dimension of an unpacked array whose size can be set or changed at run-time
 data_type  array_name [ ];
 data_type is the data type of the array elements.
 Methods for Dynamic Arrays
 new[ ]       -->  allocates the storage.
  size( )       -->  returns the current size of a dynamic array.
 delete( )    -->  empties the array, resulting in a zero-sized array.
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SystemVerilog Data Structures

 Queues: variable size, ordered collection of homogeneous elements. Queues can grow and shrink, supports adding
and removing elements anywhere
 Queues are declared using the same syntax as unpacked arrays, but specifying $ as the array size, In queue 0 represents
the first and $ represents the last entree
 Queue Declaration
  data_type queue_name[$];
  where:      
  data_type        -  data type of the queue elements.        
 queue_name    -  name of the queue.

 Mailboxes: mechanism to exchange messages between processes, data can be sent to a mailbox by one process and
retrieved by another. Very effective in testbenches to transfer packets of data between modules
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Blocking and Non-Blocking Assignments

Blocking Assignment Non-Blocking Assignments
 Executes in series order, uses ‘=’,  Executes in parallel, uses ‘<=’,
blocks execution of next assignments occur at the same
statement until completion of time (during the end of the
current assignment simulation time stamp)
 initial begin   initial begin
    //initializing a and b     //initializing a and b
    a = 10;     a = 10;
    b = 15;     b = 15;
           
    x = a + b;     x <= a + b;
    y = a + b + x;     y <= a + b + x;
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SystemVerilog Control Flow

 Unique if : evaluates all the conditions in parallel
 Priority if : evaluates all the conditions in sequential order
 Loops: While/Do While, For Loop/For each break/continue etc.,
 Repeat: executes statements for loop variable number of times
 Event Control : any change in a variable or net can be detected using the @ event
module event_ctrl;
  bit clk;
  always #2 clk = ~clk;
 
  //always block will be executed at every posedge of clk signal
  always @(posedge clk)
  begin
    $display($time,"\tInside always block");
  end
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Processes
 Fork-join : will start all the  Fork-Join_any will be un-blocked  Fork-Join_none does not wait for
processes inside it in parallel after the completion of any of the completion of Process inside
and wait for the completion of the Process the fork-join_none before
all processes following processes are executed
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Tasks and Functions

 Function : must execute in one simulation time unit, cannot
enable a Task, must have at least one input argument, returns a
single value

 Task : can contain time-controlling statements, can enable tasks

or functions, can have zero or more arguments, does not return a
value (used for performing actions during simulation time)
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Classes
 User defined data type
that includes data,
functions, and tasks
that operate on data.
Classes allow objects
to be dynamically
created, deleted assig
and accessed via object
handles.
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Modules
 Basic building block that can be used in design or verification.

 RTL Design: contains synthesizable constructs which represents

physical hardware, can be low level (logic gates) or complex (state
machines) and can instantiate other design elements.

 RTL Testbench :contains top-level RTL DUT instance, interfaces,

assertions and other components
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Constructing a Basic
Testbench Topology
in SystemVerilog
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 Department of Electrical and Computer Engineering

Transaction Class
 Field required to generate stimulus are
declared in transaction class
 Transaction class can also be used as
placeholder for the activity monitored
by monitor on DUT signals
 Generator sends transactions to be
interpreted by the driver to provide
stimulus to the DUT through the
interface
 Monitor interprets outputs of the DUT
into transactions then pushes them to
the scoreboard
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Interface
 Systemverilog construct to
encapsulate communication
between modules
 Can contain modports which
provides direction information for
module interface ports and controls
the uses of tasks and functions
within certain modules
 Shared by multiple entities (driver,
monitor, etc.)
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Driver
 Driver Class receives the
stimulus from a
generator in the form of
a transaction through a
shared mailbox

 Driver converts
transaction level data to
signal level activity
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Monitor
 Samples the Interface
signals and convert
signal level activity to
transaction level

 Sends transaction to
scoreboard via
mailbox
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Score Board
 Scoreboard receives the sampled transaction from the monitor

 Used to perform the actual verification, is the output correct?

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Generator
 Generates transactions that will be translated into stimulus for the DUT

 Sends generated transactions to driver over mailbox

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Environment
 Contains instances of the
generator, driver, monitor, and
scoreboard, connects generators
to drivers and monitors to
scoreboard with mailboxes, and
provides instance of the interface
to all

 Main task which runs a test

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Testbench and Test

 Test Bench is the top
level entity and a
module. Instantiates
the DUT, interface and
the test

 The test is a module

that instantiates the
environment and calls
its run() procedure.
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 Department of Electrical and Computer Engineering

UVM SystemVerilog
 Universal Verification Methodology
 Provides framework for modular and layered verification components
 Developed and maintained by Accellera
 Consists of class libraries that allow for robust, reusable verification
environments
 Used widely in industry for RTL verification
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 Department of Electrical and Computer Engineering

UVM Features
 Sequences : UVM gives comprehensive control on stimulus, can be developed by
randomization, layered sequences, virtual sequences etc. (sequences of transactions)

 Stimulus/sequences are kept separate from actual testbench hierarchy.

 Uses TLM instead of mailbox

 Uses modular components, Driver, Sequencers, Agents, Env etc.

 Configuration class : database where all the parameters for the testbench hierarchy are
located
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Verification Concepts
 Simulation Verification : Verify that design meets spec for a given
input stimuli

 Formal Verification : Verify that design meets spec for any valid
input stimuli
 Equivalence Checking
 Model Checking
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Model Checking
 Given a model of a system, exhaustively and automatically check
whether this model meets a given specification as described by
assertions
 Assertions are provided by the user that describe legal or illegal
behavior
 Assertions include coverage properties that help ensure thoroughness
of verification
 How to do this ? SystemVerilog Assertions (SVA)
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Why use Assertions ?

 Reducing verification time

 Catch errors earlier

 Pinpointing sources of error

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Types of Assertions
 Concurrent assertions must always be satisfied by a design.

 Temporal assertions must by satisfied by the design under certain

defined (often clock-based) conditions. These conditions can
either contain an individual set or a sequence of sets
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SVA Immediate Assertion Example

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SVA Concurrent Assertions

 SVA allows for concurrent assertions which detect behaviors over a period of time

 Evaluation of concurrent assertions are associated with clock edges

 4 Layers:
 Boolean Expression Layer : evaluates a single expression to be true or false
 Sequence Layer : sequence of Boolean expressions over time
 Property Layer : defines a behavior of the design defined elsewhere
 Assertion Layer : asserts the property
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Example :

sequence seq;
a ##2 b;
endsequence

property p;
@(posedge clk) seq;
endproperty
a_1 : assert property(p);
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Coverage:
 Coverage is used to measure tested and untested portions of the design. Defined by the
percentage of objective that have been met

 Two Types :
 Code Coverage:
 How much of the design code is exercised, Number of lines, conditions, States in FSM,
paths taken etc.
 Functional Coverage:
 User defined metric:
 Data-oriented : values of inputs and outputs
 Control-oriented Coverage : checks for sequences of behaviors
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SVA Coverage
 Defined by creating coverage points using the covergroup construct

 Cover point is an expression or a variable, each associated with a bin

 Bins increment if the condition given to that cover point is satisfied

Department of Electrical and Computer Engineering
 Department of Electrical and Computer Engineering

References
 https://www.verificationguide.com/
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