PCI LOCAL BUS

Peripheral Component Interconnect (PCI).

Introduction
A bus is a channel or path between the
components in computer. Having a high-
speed bus is as important as having a
good transmission in a car. If you have a
700-horsepower engine combined with a
cheap transmission, you can't get all that
power to the road.
 Why do I need PCI bus??
Many reasons:
PCI acts as a hardware connector for your
audio ,video and graphics of a computer
system
Connecting your TFT with your CPU requires
a hardware like a Graphic Card.so that
computer detects the screen and displays it.
 + =

Monitor detected

hardware The hardware is

inserted in cpu
 Dual Independent Bus (DIB)

Backside Bus
Frontside Bus
PCI
◦ Direct access to system
memory for connected
devices
◦ Uses a bridge to
connect to the frontside
bus and therefore to the
CPU
Typical PCI Card

                                                                                     

                                                            
A typical PCI card

PCI card – 47 pins

 PCI Revision 2.1 Features

 Processor independence
 Low-power consumption
 Burst use for all read and write transfers
 Bus speed up to 66 MHz
 64-bit bus width
 Low pin count (PCI Target: 47,PCI Initiator: 49 pins)
 Concurrent bus operation
 Bus master support
 Hidden bus arbitration
 Auto configuration
Intro to PCI Bus Operation
Key Terms
 Initiator
 — Or Master
 — Owns the bus and initiates the data transfer
 — Every Initiator must also be a Target
 Target
 — Or Slave
 — Target of the data transfer (read or write)
 Agent
 — Any initiator/target or target on the PCI bus
Intro to PCI Bus Operation
PCI Bus Clock
 All action synchronize to the PCI clock
 Clock may be any where from 0 MHz to 33 MHz and all PCI device must
be support this range
 The revision 2.1 specification define speed up to 66 MHz

Address phase
 At the same time, initiator identifiers target device and the type of
transaction
 The initiator assert the FRAME# signal
 Every PCI target device latch the address and decode it
PCI Lines
Clock and Reset
 CLK
◦ — PCI input clock
◦ — All signals sampled on rising edge
◦ — 33MHz is really 33.33333MHz (30ns clk. period)
◦ — The clock is allowed to vary from 0 to 33 MHz
 – The frequency can change “on the fly”

 RST#
◦ — Asynchronous reset
◦ — PCI device must tri-state all I/Os during reset
Transaction Control
Target Signals
 TRDY# – I/O
◦ — “T-Ready”
◦ — When the target asserts this signal, it tells the
initiator that it is ready to send or receive data
 STOP# – I/O
◦ — Used by target to indicate that it needs to
terminate the
◦ transaction
Transaction Control
Target Signals
 DEVSEL# – I/O
◦ — Device select
◦ — Part of PCI’s distributed address decoding
 – Each target is responsible for decoding the address
associated with each transaction
 – When a target recognizes its address, it asserts
DEVSEL# to claim the corresponding transaction
Transaction Control
Initiator Signals
 FRAME# – I/O
◦ — Signals the start and end of a transaction
 IRDY# – I/O
◦ — “I-Ready”
◦ — Assertion by initiator indicates that it is ready to
send receive data
Transaction Control
Configuration Signals
 Uses the same signals as the target, plus . . .
 IDSEL – I
◦ — “ID-Sel”
◦ — Individual device select for configuration – one
unique IDSEL line per agent
◦ — Solves the “chicken-and-egg” problem
◦ – Allows the system host to configure agents before
these agents know the PCI addresses to which
they must respond
Address and Data Signals
 AD[31:0] – I/O
◦ — 32-bit address/data bus
◦ — PCI is little endian (lowest numeric index is LSB)
 C/BE#[3:0] – I/O
◦ — 4-bit command/byte enable bus
◦ — Defines the PCI command during address phase
◦ — Indicates byte enable during data phases
 – Each bit corresponds to a “byte-lane” in AD[31:0] – for
example,C/BE#[0] is the byte enable for AD[7:0]
Address and Data Signals
 PAR – I/O
◦ — Parity bit
◦ — Used to verify correct transmittal of address/data
and command/byte-enable
◦ — The XOR of AD[31:0], C/BE#[3:0], and PAR
should return zero (even parity)
 – In other words, the number of 1’s across these 37
signals should be even
Arbitration Signals
For initiators only!
REQ# – O
◦ — Asserted by initiator to request bus ownership
◦ — Point-to-point connection to arbiter – each initiator has its
own REQ# line
GNT# – I
◦ — Asserted by system arbiter to grant bus ownership to the
initiator
◦ — Point-to-point connection from arbiter – each initiator has
its own GNT# line
Error Signals
 PERR# – I/O
◦ — Indicates that a data parity error has occurred
◦ — An agent that can report parity errors can have
its PERR# turned off during PCI configuration
 SERR# – I/O
◦ — Indicates a serious system error has occurred
 – Example: Address parity error
◦ — May invoke NMI (non-maskable interrupt, i.e., a
restart) in some systems
PCI Addressing
and Bus Commands
PCI Address Space
 A PCI target can implement up to three different
types of address spaces
— Configuration space
◦ – Stores basic information about the device
◦ – Allows the central resource or O/S to program a device
with operational settings
— I/O space
◦ – Used mainly with PC peripherals and not much else
— Memory space
◦ – Used for just about everything else
Types of PCI Address Space
 Configuration space
— Contains basic device information, e.g., vendor or
class of device
— Also permits Plug-N-Play
◦ – Base address registers allow an agent to be mapped
dynamically into memory or I/O space
◦ – A programmable interrupt-line setting allows a software
driver to program a PC card with an IRQ upon power-up
(without jumpers!)
Types of PCI Address Space
Configuration space (cont’d)
— Contains 256 bytes
◦ – The first 64 bytes (00h – 3Fh) make up the
standard configuration header, predefined by the
PCI spec
◦ – The remaining 192 bytes (40h – FFh) represent
user-definable configuration space
 • This region may store, for example, information specific
to a PC card for use by its accompanying software driver
IO Space
— This space is where basic PC peripherals
(keyboard, serial port,etc.) are mapped
— The PCI spec allows an agent to request 4
bytes to 2GB of I/O space
◦ – For x86 systems, the maximum is 256 bytes
because of legacy ISA issues
Memory Space
 Memory space
— This space is used by most everything else – it’s
the general-purpose address space
◦ – The PCI spec recommends that a device use memory
space, even if it is a peripheral
— An agent can request between 16 bytes and 2GB
of memory space
◦ – The PCI spec recommends that an agent use at least 4kB
of memory space, to reduce the width of the agent’s
address decoder
PCI Commands
 PCI allows the use of up to 16 different 4-bit
commands
◦ — Configuration commands
◦ — Memory commands
◦ — I/O commands
◦ — Special-purpose commands
 A command is presented on the C/BE# bus by the
initiator during an address phase (a transaction’s first
assertion of FRAME#)
PCI Commands
PCI Configuration
The Plug-and-Play Concept
Plug-and-Play (PNP)
— Allows add-in cards to be plugged into any slot
without changing jumpers or switches
◦ – Address mapping, IRQs, COM ports, etc., are assigned
dynamically at system start-up
— For PNP to work, add-in cards must contain basic
information for the BIOS and/or O/S, e.g.:
◦ – Type of card and device
◦ – Memory-space requirements
◦ – Interrupt requirements
Configuration Transactions
 Are generated by a host or PCI-to-PCI bridge
 Use a set of IDSEL signals as chip selects
◦ — Dedicated address decoding
◦ — Each agent is given a unique IDSEL signal
 Are typically single data phase
◦ — Bursting is allowed, but is very rarely used
 Two types (specified via AD[1:0] in addr. phase)
◦ — Type 0: Configures agents on same bus segment
◦ — Type 1: Configures across PCI-to-PCI bridges
Why PCI-X 2.0?
Bus Bandwidths
PCI-X 2.0 Write - Example
Comparing AGP,PCI and PCI
Express
Peripheral Component Interconnect
(PCI)
 A local bus standard
developed by Intel
Corporation
 Used by most modern PCs
in addition to a more
general ISA expansion bus
 A 64-bit bus
 Can run at clock speeds of
33 or 66 MHz
Accelerated Graphics Port (AGP)
 Developed by Intel
Corporation
 Introduces a point-to-point
channel so that the graphics
controller can directly
access main memory
 Channel is 32 bits wide and
runs at 66 MHz
 Total bandwidth of 266
MBps
PCI EXPRESS
 An I/O interconnect bus
standard
 Expands on and doubles the
data transfer rates of
original PCI
 Includes a protocol and a
layered architecture
 Carries data in packets
along 2 pairs of point-to-
point data lanes
 Advantages of AGP over PCI
Faster communication takes place because of
pathway between slot and processor.
It uses sideband addressing. This results in
improved overall AGP data throughput.
AGP card is capable of reading textures
directly from system RAM using the Graphics
Address Remapping Table (GART).
Advantages of PCI Express over PCI
Serial technology providing scalable
performance.
 Point-to-point link dedicated to each device,
instead of the PCI shared bus.
Opportunities for lower delay in server
architectures, because PCI Express provides a
more direct connection to the chip set
Northbridge.
Small connectors and, in many cases, easier
implementation for system designers.
Advantages of PCI Express over AGP
It can handle a greater data throughput than an
AGP slot.
Offers performance of up to 4 times faster than
the fastest AGP slot.
You can connect more than one video card to
your computer for extra performance. Not
possible with AGP, since a motherboard can
only ever have one AGP slot.
It's cheaper than AGP to implement at the board
level.
Thank You

-Navil Fernandes
-Noel D’souza