Microprocessor & Interfacing

Tittle: interfacing pheripheral 8251 with 8086

Section 4
NAME ID
1.Odaa Mitiku.........................A/UR14342/10
2.Workisa Tilehun.....................A/UR14344/10
3.Jalle Lijalem........................A/UR14280/10
4.Tullu Kebede........................A/UR14400/10
5.Sirressa Ete.........................A/UR14393/10
6.Khelifa abdela......................A/UR14265/10
Contents:
 Introduction
 Block diagram of 8251
 Contents of block diagram
 Initializing the 8251
 Interfacing the 8251 with 8086.
8251
INTRODUCTION:
The 8251A is a programmable serial communication interface chip designed for
synchronous and asynchronous serial data communication.
 It supports the serial transmission of data.
 Serial communication is the common method of data transfer between
computer and peripherals.
 serial data transmit one at a time.
Transmit data

Receive data

System 1 System 2
clk

Signal common
 It is packed in a 28 pin DIP.

 It is possible to use either of the two

methods.
 UART: universal asynchronous
receiver/ transmitter
 USART: universal
Synchronous/Asynchronous
Receiver/Transmitter
Block Diagram of 8251
 The block diagram contains:
Read/Write Control Logic
 Modem Control
 Transmitter

 Receiver

 Data Bus buffer

 Data Bus Buffer
 D0-D7 : 8-bit data bus used to read or write status, command word or
data from or to the 8251A
 Read/Write Control logic
 Includes a control logic, six input signals & three buffer registers: Data
register, control register & status register.
 Control logic : Interfaces the chip with MPU, determines the functions of
the chip according to the control word in the control register & monitors
the data flow.
Input signals
 CS – Chip Select : When signal goes low, the 8251A is selected by the MPU for
communication.
 C/D – Control/Data : When signal is high, the control or status register is
addressed; when it is low, data buffer is addressed.
 WR : When signal is low, the MPU either writes in the control register or
sends output to the data buffer.
 RD : When signal goes low, the MPU either reads a status from the status
register or accepts data from data buffer.
 RESET : A high on this signal reset 8252A & forces it into the idle mode.
 CLK : Clock input, usually connected to the system clock for communication
with the microprocessor.

Control Register
 16-bit register for a control word consist of two independent bytes namely
mode word & command word.
 Mode word : Specifies the general characteristics of operation such as baud,
parity, number of bits etc.
 Command word : Enables the data transmission and reception.
 Register can be accessed as an output port when the Control/Data pin is
high.
Status register
 Checks the ready status of the peripheral.
 Status word in the status register provides the information concerning
register status and transmission errors.
Data register
 Used as an input and output port when the C/D is low
Modem Control
 DSR - Data Set Ready : Checks if the Data Set is ready when communicating with a
modem.
 DTR - Data Terminal Ready : Indicates that the device is ready to accept data when
the 8251 is communicating with a modem.
 CTS - Clear to Send : If its low, the 8251A is enabled to transmit the serial data
provided the enable bit in the command byte is set to ‘1’.
 RTS - Request to Send Data : Low signal indicates the modem that the receiver
is ready to receive a data byte from the modem.
8251 receiver

• The receiver section: whenever RxD line goes low, control

assumes it is a start bit, waits for half bit time and samples again.
• responsible for reading the serial bit stream of data atRxD(receive data) input
and converting it into parallel form.
• RxRDY(receive ready) output switched to logic 1 level to tell the
microprocessor that a char. is available and is sitting inside the USART and
should be read from the receive –buffer register.
• RxC Receiver Clock. Controls the rate which bits are received by the USART. In
Asynchronous Mode, the clock can be set to 1,16 or 64 times the baud.
8251 transmitter
 Transmitter section receives parallel data from the microprocessor over the
data bus.
 Finally, it is shifted out of this register to produce a bit serial output on the TxD
line.
 TxRDY is switched to logic 1 when the transmit buffer register is empty.
 TxE transmitter Empty –This is an output signal. Logic 1 on this line indicates the
output register is empty. Reset when a byte is transferred from the buffer to output
registers.
 TxC Transmitter Clock. Controls the rate which bits are transmitted by the USART.
The clock can be set to 1,16 or 64 times the baud (using Mode Word –next slide)
Initializing the 8251
 To implement serial communication the MPU must inform the 8251 about the
mode, baud, stop bits, parity etc. A set of control words must be loaded.
 Mode Words
 Specifies general characteristics of the operation.
 Command Words
 Enables the data transmission and/or reception
 Status Word provides the information concerning register status and transmission
errors.
 8251 can be reset internally by using the Internal Reset Bit D6.
INTERFACING 8251A TO 8086 PROCESSOR
The 8251A is used here as a peripheral device for serial communication and is
programmed by the CPU to operate
8251 accepts data characters from the CPU in parallel format and then converts
them into a continuous serial data stream for transmission.
Simultaneously, it can receive serial data streams and convert them into parallel
data characters for the CPU..
Microprocessor don’t have the direct serial communications, so to communicate
the data serially to a device we need a driver to send a character serially, here we
use 8251.
Pin Assignment with 8086
MORE on INTERFACING 8251A TO 8086 PROCESSOR
• The chip select for I/O mapped devices are generated by using a 3-to-8
decoder.
• The address lines A5, A6 and A7 are decoded to generate eight chip select
signals (IOCS-0 to IOCS-7) and in this, the chip select signal IOCS-2 is used to
select 825lA.
• The address line A0 and the control signal M/IO(low) are used as enable for
decoder.
• The line A1 of 8086 is connected to C/D(low) of 8251A to provide the internal
addresses.
• The lines D0 – D7 connected to D0 – D7 of the processor to achieve parallel data
transfer.
• The RESET and clock signals are supplied by 8284 clock generator. Here the
Processor clock is directly connected to 8251A.
• 8251A in I/O mapped in the system is shown in the figure.
Block diagram of the
interfacing
• The peripheral clock (PCLK) supplied by 8284, is divided by suitable clock
dividers like programmable timer 8254 and then used as clock for serial
transmission and reception.
• In 8251A the transmission and reception baud rates can be different or same.
• The TTL logic levels of the serial data lines and the control signals necessary for
serial transmission and reception are converted to RS232 logic levels using MAX232
and then terminated on a standard 9-pin D-.type connector.
• The device, which requires serial communication with processor, can be
connected to this 9-pin D-type connector using 9-core cable.
• The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to
initiate interrupt driven data transfer scheme between processor and 8251 A.
• The I/O addresses allotted to the internal devices of 8251A are listed in table.
 OBJECTIVE
 8251 is interfaced with 8086 and used for serial communication.
 Microprocessor don’t have the direct serial communications, so to communicate
the data serially to a device we need a driver to send a character serially, here
we use 8251.
 Demo for the assembly code using emu8086
Q: Write an ALP to interface 8251 with 8086. Transfer some data from 8086 memory
at some location to another location in the memory through 8251.

0000:1000 MOV AL, 4D ;Mode word 0000:1018 IN AL, 29 ;status word of reciever
0000:1002 OUT 29, AL ;for port B 0000:101A TEST AL, 02 ;rx rdy
0000:1004 OUT 31, AL ;for port A 0000:101C JZ 1018 ;loop if reciever not
ready
0000:1006 MOV AL, 27 ;CW
0000:101E IN AL, 28 ;accept the data from
0000:1008 OUT 29, AL ;port B
reciever
0000:100A OUT 31, AL ;port A
0000:1020 MOV [DI], AL ;mov this data to the
0000:100C MOV CL, 09 ;counter for nine nos destination
0000:100E MOV SI, 2000 ;location for source 0000:1022 INC SI ;increment and decrement
data counters
0000:1011 MOV DI, 5000 ;location for 0000:1023 INC DI
destination data
0000:1024 DEC CL
0000:1014 MOV AL, [SI] ; contents of si moved
0000:1026 JNZ 1014 ;Repeat these steps for
to al
the next number
0000:1016 OUT 30, AL ;data sent to port A
0000:1028 INT 3 ;Exit
transmitter
Demo for the assembly code using emu8086
to Interface Bluetooth with 8086 with 8251.

 Assembly Program to transmit data

in 8086

Title : Program to transmit a

character from 8086 through
bluetooth
1100 Be 00 15 MOV SI,1500H
1103 B0 36 MOV AL,36H
1105 BA 06 FF MOV DX,FF06
1108 EE OUT DX,AL
1109 B0 40 MOV AL,40H
110B BA 04 FF MOV DX,FF04
110E EE OUT DX,AL
110F B0 01 MOV AL,01H
1111 BA 04 FF MOV DX,FF04
1114 EE OUT DX,AL
1115 B1 05 RELOAD: MOV CL,05H
1117 BA 12 FF CHECK: MOV
DX,FF12
111A EC IN AL,DX
Assembly Demo using Proteus
 conclusion
 The 8251A is used here as a peripheral device for serial communication
and is programmed by the CPU to operate using virtually any serial data
transmission technique.
 We can interface peripheral ic (8251) in order to make a serial
communication with another device.