Chap 8. Sequencing and Control

Chap 8.
Sequencing and Control
Fall 2000
Jaeyoung Choi
choi@comp.soongsil.ac.kr
8.1 Introduction Chap.8
2
 binary information in a digital computer can be classified

as either data or control information
 data
 manipulated in a datapath with ALUs, registers, multi
plexers, and buses
 control
 provide signals that activate the various microoperations & determi
ne the sequence in which the various actions are performs
 timing of all registers in a synchronous digital system is controlled
 by a master clock generator

 binary variables that control the selection inputs of multiplexers, bus
es, ALUs, & load control inputs of registers are generated b
y the control unit
3
 Control unit is a sequential circuit with state that dictate

the control signals for the system
 using status conditions and control inputs,
the sequential control unit determines the next state,
in which additional microoperations are activated
 2 distinct types of control units:

programmable system & nonprogrammable system
4
 programmable system
 a portion of the input consists of a sequence of instructions
 each instruction specifies the operation the system is to perform
 instructions are stored in memory (RAM or ROM)
 program counter
 provide the address in memory of the instructions to be executed
 address comes from a register called PC
 executing an instruction
 activating the necessary sequence of microoperations in the datapath
that are required to perform the operation specified by the instructi
on
 nonprogrammable system
 control unit is not responsible for obtaining instructions, nor for seq
uencing the execution of those instructions
 control unit determines the operation to be performed & the seq
uence of those operations, based on only its inputs and the status bits
8.2 Algorithmic State Machines Chap.8
5
 a data-processing task
 register transfer operations controlled by a sequencing machanism
 can be specified as a hardware algorithm t
hat consists of a finite number of procedural steps
which perform the data processing task
 flowchart
 a convenient way to specify a sequence of procedural steps
& decision paths for an algorithm
 ASM (Algorithmic State Machine)

 resembles a conventional flowchart,
but it describes a sequence of events, a
s well as the timing relationship between the states & actions
6
 ASM Chart Elements

a) state box :- register transfer operations or output signals
c) decision box :- describes the effect of inputs on the control
d) conditional ouput box :- from decision box
7
 ASM Block Example
 ASM chart
 form of state
diagram for the
sequential circuit
part of
the control unit
8
 ASM Timing Consideration

8.3 Decision Example: Binary Multiplier Chap.8
9
 introduce a hardware algorithm for binary multiplication, pr

opose a simple datapath for its implementation,
& then describe its register transfers and control by use of an ASM
 multiplies 2 unsigned binary numbers
 Binary Multiplier
 a copy of the multiplicand is added
to a partial product
& the partial product is stored
in a register for the shift action
 the partial product is shifted
to the right
(adder is needed for only n bit
positions instead of 2n bit)
10
 Hardware Multiplication Example

11
 Block Diagram for Binary Multiplier

12
 multiplicand is loaded into register B from IN

 multiplier is loaded into register Q from IN
 partial product is formed in reg A, & stored in reg A & Q
 C F-F stored the carry Cout & shifted

into the MSB of A,
 LSB of A is shifted into the MSB of Q,
& LSB of Q is discarded
 Q0 holds the bit of the multiplier that must be considered next
 counter P
 count the number of add-shift or shift actions
 initially set to n-1 & counted down
13
 ASM Chart for Multiplier
 [IDLE]:
 multiplication process starts wh
en G becomes 1
(ASM moves from state IDLE
to state MUL
0)
 [MUL0]:
 a decision is made based on Q0
 [MUL1]:
 a right shift is performed on
C, A, & Q
 C  0, A(n-1)  C, A  sr A, Q
(n-1)  A(0), Q  sr Q
or C  A  Q  sr C  A  Q
8.4 Hardwired Control Chap.8
14
 2 distinct aspects to deal with

 control of the microoperations
 part of the control that generates the control signals
 ASM table that defines the control signals i
n terms of states & inputs
 sequencing of the control unit & microoperations

 part of the control that determines what happens next
 a simplified ASM chart that represents only transitions f
rom state to state
15
 Control signals for binary multiplier

 based on the ASM chart
16
 Sequencing Part of ASM Chart

 information on sequencing is represen
ted with information on microoperati
ons removed
 conditional output boxes are removed

 decision box not affecting the next s
tate is removed
 design the sequencing part of the con
trol unit with the ASM chart i.e. t
he part that represents the next-sta
te behavior
17
 Sequence Register and Decoder

 provide an output signal corresponding to each of the states
 A register with n F-Fs can have up to 2n states
& n-to-2n decoder has up to 2n outputs, one for each of the states
 consist of 3 states and 2 inputs
 2 F-Fs and 2-to-4-line decoder
18
 state table for the sequencing part

 designate 2 F-Fs as M1 & M0
 state 00 (IDLE), 01 (MUL0), 10 (MUL1)
 input equations for F-Fs
DM0 = IDLE • G + MUL1 • Z' & DM1 = MUL0
19
 One Flip-Flip per state

 another possible method
of control logic de
sign
 a F-F is assigned to
each of the state,
 only one of F-F conta
ins a 1, wit
h others 0
20
 Control unit with

one flip-flop per state
8.7 Microprogrammed Control Chap.8
21
 microprogrammed control
 a control unit with its binary valu
es stored as words in memory
 microinstructions
 one or more microinstructions
 microprogram
 fixed at the time of the system d
esign & stored in ROM
22
 contents of a word in ROM specify the microoperations to be per

formed for both the datapath & the control unit
 CAR (control address register)
 specifies address of microinstruction
 CDR (control data register)
 holds the microinstructions currently being executed by the da
tapath and the control unit
 next-address generator
 produce the next address, depending on inputs (status bits)
 sequencer
 next-address generator combined with CAR
 CDR holds the present microinstruction while the next address is b
eing computed & the next microinstruction is being read from memo
ry
 status bits enter the next-address generator & affect the det
ermination of the next state
Chap.8
23
8.7 Microprogramm
ed Control
24
 4 control signals are needed for the datapath

 Initialize, Load, Clear_C, & Shift_dec
 4 control signals can be used as given or

can be encoded to reduce the number of bits in microinstruction
25
 3 control signal combinations are used

 (Initialize, Clear_C) in state INIT
 (Load) in state ADD
 (Clear_C, Shift_dec) in state MUL1
 format of the microinstruction control word
 DATAPATH :- 4-bit code

 NXTADD0, NXTADD1 :- define the next addresses based on decision
 SEL :- select whether to make a decision
if so, to select which one of the three decision variables G, Q 0, Z

26
27
Design a control unit

 length of ROM co
ntrol words :- 12 b
its
 ROM contains 5 w
ords (since there
are only 5 status)
 microprogrammed
control unit
28
 a microprogram for the binary multiplier in register transfer notation

 microinstruction corresponds to each of the state in ASM chart
29
 left: the register transfer microprogram

 a symbolic microprogram
 right: the symbolic microprogram
 a binary microprogram
8.8 A Simple Computer Architecture Chap.8
30
 Program
 Instruction
 Opcode (Operation code)
 2m tane opcode için m bit
kullanmak yeterli.
Explicitly instruction; hedef registeri açık olarak komutta belirtilir.
R1 R2+R3
Implicitly instruction; hedef dolaylı olarak belirtilir;
R1  R1+1 (INC R1)

31
“Jump” ve “branch” ta işaretli sayılar kullanılır!

32
33
Chap.8
34
8.9 Single Cycle

Hardwired Control
8.9 Single Cycle Hardwired Control Chap.8
35
36
37
38
Max clock freq.=58.8MHz
Single cycle computer
Hardwired and Microprogrammed

control , they require multiple cycle, can
not be implemented

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Chap 8.

Sequencing and Control

 binary information in a digital computer can be classified

 timing of all registers in a synchronous digital system is controlled

 by a master clock generator

 Control unit is a sequential circuit with state that dictate

 2 distinct types of control units:

 ASM (Algorithmic State Machine)

 ASM Chart Elements

 ASM Block Example

 ASM Timing Consideration

 introduce a hardware algorithm for binary multiplication, pr

 Hardware Multiplication Example

 Block Diagram for Binary Multiplier

 multiplicand is loaded into register B from IN

 C F-F stored the carry Cout & shifted

 Q0 holds the bit of the multiplier that must be considered next

 ASM Chart for Multiplier

 2 distinct aspects to deal with

 sequencing of the control unit & microoperations

 Control signals for binary multiplier

 Sequencing Part of ASM Chart

 conditional output boxes are removed

 Sequence Register and Decoder

 state table for the sequencing part

 One Flip-Flip per state

 Control unit with

 contents of a word in ROM specify the microoperations to be per

 4 control signals are needed for the datapath

 4 control signals can be used as given or

 3 control signal combinations are used

 format of the microinstruction control word

 DATAPATH :- 4-bit code

if so, to select which one of the three decision variables G, Q 0, Z

Design a control unit

 a microprogram for the binary multiplier in register transfer notation

 left: the register transfer microprogram

Explicitly instruction; hedef registeri açık olarak komutta belirtilir.

R1  R1+1 (INC R1)

“Jump” ve “branch” ta işaretli sayılar kullanılır!

8.9 Single Cycle

Max clock freq.=58.8MHz

Single cycle computer

Hardwired and Microprogrammed

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