Timing Diagram of

8085
Timing Diagram is a graphical representation. It
represents the execution time taken by each
instruction in a graphical format. The execution
time is represented in T-states.

Instruction Cycle:
The time required to execute an instruction .

Machine Cycle:
The time required to access the memory or
input/output devices .

T-State:
•The machine cycle and instruction cycle takes
multiple clock periods.
•A portion of an operation carried out in one
system clock periodcollected
is called as T-state.
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collected by C.Gokul AP/EEE,VCET
 Timing diagrams
• The 8085 microprocessor has 7 basic machine
cycle. They are
1. Op-code Fetch cycle(4T or 6T).
2. Memory read cycle (3T)
3. Memory write cycle(3T)
4. I/O read cycle(3T)
5. I/O write cycle(3T)
6. Interrupt Acknowledge cycle(6T or 12T)
7. Bus idle cycle
collected by C.Gokul AP/EEE,VCET
collected by C.Gokul AP/EEE,VCET
1.Opcode fetch cycle(4T or
6T)
 OPCODE
• The Opcode fetch cycle, fetches the instructions from

FETCH
memory and delivers it to the instruction register of the
• microprocessor
Opcode fetch machine cycle consists of 4 T-states.
T1 State:
During the T1 state, the contents of the program counter are
placed on the 16 bit address bus. The higher order 8 bits are
transferred to address bus (A8-A15) and lower order 8 bits are
transferred to multiplexed A/D (AD0-AD7) bus.
ALE (address latch enable) signal goes high. As soon as
ALE goes high, the memory latches the AD0-AD7 bus. At
the middle of the T state the ALE goes low
T2
State:
During the beginning of this state, the RD’ signal goes
low to enable memory. It is during this state, the selected
memory location is placed on D0-D7 of the Address/Data
multiplexed bus.
T3 State:
In the previous state the Opcode is placed in D0-D7 of the
A/D bus. In this state of the cycle, the Opcode of the A/D
bus is transferred to the instruction register of the
microprocessor. Now the RD’ goes high after this action and
thus disables the memory from A/D bus.
T4 State:
In this state the Opcode which was fetched from the
memory is decoded.
2. Memory read cycle
(3T)
• These machine cycles have 3 T-
states.
T1 state:
• The higher order address bus (A8-A15) and lower order
address and data multiplexed (AD0-AD7) bus. ALE goes high so
that the memory latches the (AD0-AD7) so that complete 16-
bit address are available.
The mp identifies the memory read machine cycle from the
status signals IO/M’=0, S1=1, S0=0. This condition indicates the
memory read cycle.
T2 state:
• Selected memory location is placed on the (D0-D7) of the A/D
multiplexed bus. RD’ goes LOW
T3 State:
• The data which was loaded on the previous state is transferred
to the microprocessor. In the middle of the T3 state RD’ goes
high and disables the memory read operation. The data which
3. Memory write cycle
(3T)
• These machine cycles have 3 T-
states.
T1 state:
•The higher order address bus (A8-A15) and lower order
address and data multiplexed (AD0-AD7) bus. ALE goes high so
that the memory latches the (AD0-AD7) so that complete 16-
bit address are available.
The mp identifies the memory read machine cycle from the
status signals IO/M’=0, S1=0, S0=1. This condition indicates the
memory read cycle.
T2 state:
•Selected memory location is placed on the (D0-D7) of the A/D
multiplexed bus. WR’ goes LOW
T3 State:
•In the middle of the T3 state WR’ goes high and disables the
memory write operation. The data which was obtained from
the memory is then decoded.
4.I/O read cycle(3T)
5.I/O write cycle(3T)
STA instruction
ex: STA 526A
It require 4 m/c
cycles13 T states
1.opcode fetch(4T)
2.memory read(3T)
3.memory read(3T)
4.Memory
write(3T)
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 Timing diagram for IN C0H
• Fetching the Opcode DBH from the
memory 4125H.
• Read the port address C0H from 4126H.
• Read the content of port C0H and send it
to the accumulator.
• Let the content of port is 5EH.
 It require 3 m/c
cycles 10 T states

opcode fetch(4T)
memory read(3T) I/O
read(3T)

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collected by C.Gokul AP/EEE,VCET
 OUT
instruction
Machines
1.instruction
Cycles(10T):
fetch(4T) 2.memory
read (3T)
3.IO write (3T)
 Timing diagram for MVI B, 43h
• Fetching the Opcode 06H from the
memory 2000H. (OF machine cycle)
• Read (move) the data 43H from memory
2001H. (memory read)

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collected by C.Gokul AP/EEE,VCET
INR M
ADD M
 Let us consider the following sample code for a better explanation –

Addres Hex Mnemoni Comment

s Codes c

Mnemonics, Operand Opcode(in HEX) Bytes

2000 31 LXI SP, SP ← 5000H.Initializing the SP
5000H

2001 00 Low order Byte of the address

2002 50 High order Byte of the address

2003 3E MVI A, A ← 00H, Initializing the Accumulator

00H

2004 00 00H as operand

2005 06 MVI B, B ← 01H

01H

2006 01 01H as operand

2007 0E MVI C, C ← 02H

02H

2008 02 02H as operand

2009 16 MVI D, D ← 03H

CALL Label CD 3
03H

200A 03 03H as operand

200B CD CALL Calling the subroutine at address 2013H.

2013H So now the control of the program will be
transferred to the location2013H. And the
return address 200EH i.e. address of the
next instruction will be pushed on the top
of the stack. As a result4FFFH (SP – 1) will
contain 20H and 4FFEH (SP – 2) will
contain 0EH respectively.

200C 13 Low order Byte of the address

200D 20 High order Byte of the address

200E 21 LXI H, HL ← 4050H,Initializing the HL register

4050H pair. After execution of the RETinstruction,
control will come back to this instruction.
4050Hwill have the value 06H, i.e. the
final sum of 01H + 02H + 03H =06H

RET C9 1
200F 50 Low order Byte of the address

2010 40 High order Byte of the address

2011 77 MOV M, M ← A, Content of the Accumulator will

A be transferred to the memory location
4050H as it is pointed by HL register pair

2012 76 HLT End of the program.

2013 80 ADD B A←A+ B

2014 81 ADD C A←A+ C

2015 82 ADD D A←A+ D

2016 C9 RET Return the control to the address 200EH.

Return address 200EH will be popped out
from the top of the stack.  So from address
4FFEH, 0EH will be popped and from
address 4FFFH 20Hwill be popped and SP
will get the initial address 5000H back as
its content accordingly
 5000H

2001 00 Low order Byte of the address

2002 50 High order Byte of the address

2003 3E MVI A, A ← 00H, Initializing the

00H Accumulator

2004 00 00H as operand

2005 06 MVI B, B ← 01H

01H

2006 01 01H as operand

2007 0E MVI C, C ← 02H

02H

2008 02 02H as operand

 References
• www.slideshare.net
• www.docstoc.com
• www.slideworld.com
• www.nptel.ac.in
• www.scribd.com
• http://opencourses.emu.edu.tr/
• http://engineeringppt.blogspot.in/
• http://www.pptsearchengine.net/
• www.4shared.com
• http://8085projects.info/
Books:
Microprocessors and microcontrollers by
krishnakanth Microprocessors and microcontrollers
collected by C.Gokul AP/EEE,VCET
by Nagoor Kani
 Staff references
• 8085 microprocessor by Sajid Akram, researcher/lecturer at c.abdul
hakeem college of engineering and technology
• Timingdiagram by puja00 (slideshare.net)
• Microprocessor 8086 by Gopikrishna Madanan, Assistant Professor of
Physics at Collegiate Education, Kerala, India

collected by C.Gokul AP/EEE,VCET