LOGIC SYNTHESIS

Presentation by
SUDHIR KUMAR MADHI
 Goals of Synthesis

• Synthesis is process of converting RTL (Synthesizable Verilog code)

to technology specific gate level netlist (includes nets, sequential and
combinational cells and their connectivity).
1.To get a gate level netlist
2.Inserting clock gates
3.Logic optimization
4.Inserting DFT logic
5.Logic equivalence between RTL and netlist should be maintained
 Input files required

1.Tech related:
.tf- technology related information.
.lib-timing info of standard cell & macros
2.Design related:
.v- RTL code.
SDC- Timing constraints.
UPF- power intent of the design.
Scan config- Scan related info like scan chain length, scan IO, which flops are
to be considered in the scan chains.
3.For Physical aware:
• RC co-efficient file (tluplus).
• LEF/FRAM- abstract view of the cell.
• Floorplan DEF- locations of IO ports and macros
 Types of Synthesis
• 1. Logical Synthesis
• Logical synthesis is a conventional synthesis, that
processes the HDL (Verilog or VHDL) design and
generates gate level netlist. During this process, the
compiler optimizes the design based on predefined
constraints.
 2. Physical Aware Synthesis
• Physical Aware synthesis requires additional floorplan
DEF as an input. Floorplan DEF contains physical
information like IO ports placements, macro placement
information, blockages information and die area
information. Additionally, we use RC co-efficient file as
one of the inputs to compute a more accurate wire
delay values compared to the WLM (Wire Load Model)
method
 Advantages of Physical Aware
synthesis:
1.Better PPA (Power, Performance, Area).
2.Better timing correlation with PNR.
3.Better turnaround time (reduces the number of
iterations).
 Synthesis input
1.LIB: The timing library (.lib) contains information related to the timing,
power, and area of standard cells. It also contains different PVT
characterizations of cells.
2.LEF: LEF represents the physical information of metal and via, standard cell,
and macro.
3.RTL: It’s a descriptive code written in HDL format.
4.SDC: It represents the design constraint.
5.DEF: DEF file contains the placement information of macro, pre-placed cells,
IO ports, block size, and blockages. Mainly used for the Physical Aware
synthesis.
6.UPF: UPF file is required to describe the power intent of the design including
the power domain, level shifter, isolation cell, and retention registers.
 1. Analyze

• Checks syntax on RTL and generates immediate files.

2. Elaborate
• Brings all lower level blocks into synthesis tool.
• All the codes and arithmetic operators are converted into Gtech and
DW (Design Ware) components. These are technology independent
libraries.
• Gtech- contains basic logic gates &flops.
• DesignWare- contains complex cells like FIFO, counters.
• Elaborate performs following tasks;

• Analyses design hierarchy.

• Removes empty switches and dead branches.
• Executes initial commands.
• Detects asynchronous reset.
• Converts decision trees to mux.
• Converts synchronous to Dlatch/DFF.
• FSM pass
• Detects FSM logic and extracts the no of input, output bits and state bits.
• Converts FSM logic to basic logic.
 Elaboration
• At this stage, it reads the RTL code, and this RTL code is
converted into modules as per its logical hierarchy. Once it has all
logical Boolean representation loaded, the tool maps logic with a
technology-independent cell called the Gtech cell.
• During elaboration, the tool checks whether the design is unique,
if not, it stops the tool. Once the design becomes unique, the tool
checks for unresolved references in the design. If it has linking
issues, then an RTL correction is required, or you need to check if
it is due to any missing libraries. After elaboration, it checks for
timing loops in design. If you find any timing loop, you need to get
RTL correction done by the designer.
• Memory pass
• Merging DFF to memory write(memwr) and memory read (memrd)
• Consolidating memwr/memrd cells
• Generate memory (mem) cells
• Mapping mem cells to basic logic
 3. Import constraints and UPF

• Once the design is extracted in the form of technology independent

cells, timing constraints are imported from the SDC file.
• If the design consists of multiple power domains, then using the UPF
power domains, isolation cells, level shifters, power switches,
retention flops are placed.
 4. Clock gating

• Due to high switching activity of clock a lot of dynamic power is

consumed. One of the techniques to lower the dynamic power is clock
gating. In load enabled flops, the output of the flops switches only
when the enable is on. But clock switches continuously, increasing the
dynamic power consumption.
• By converting load enable circuits to clock gating circuit dynamic
power can be reduced. Normal clock gating circuit consists of an AND
gate in the clock path with one input as enable. But when enable
becomes one in between positive level of the clock a glitch is
obtained.
 Fig2: Load enabled register bank

Fig3: Clock gated register bank

Fig4: Waveform for clock gate
To remove the glitches due to AND gate, integrated clock gate is used. It has a negative triggered latch and an AND gate.

Fig5: Integrated clock gated register bank

 Fig6: Waveform for ICG

Clock gating makes design more complex. Timing and CG timing closure becomes complex. Clock gating adds more gates to
the design. Hence min bit width (minimum register bit width to be clock gated) should be wisely chosen, because the overall
dynamic power consumption may increase.
• 5. Compile
• Performs Boolean optimization.
• Maps all the cells to technology libraries.
• Performs logic and design optimization.
• Logic optimization
• Constant folding
• Detect identical cells
• Optimize mux(dead branches in mux)
• consolidate mux and reduce inputs(many to single)
• Remove DFF with constant value
• Reduce word size of the cells
• Remove unused cells and wires
 Compile and optimization
• After elaboration, in the compilation stage, the tool maps the Gtech cell
with the actual cell (specific technology dependent) from the library.
Actual cell mapping is dependent on the design constraints or user-specific
constraints. Apart from this, the tool removes the registers with constant

• propagation/unloaded which are not required in the design. If these

removed cells are required, then you need to provide feedback to the
designer to get the correct RTL.

• After elaboration and compilation, the tool performs optimizations based

on user constraints to meet timing, area, and power requirements.
• Design optimization
• Reduce TNS and WNS
• Power Optimization
• Area Optimization
• Meet the timing DRV’s
• incremental clock gating
• 7. DFT (Design for Testing) insertion
• DFT circuits are used for testing each and every node in the design.
• More the numbers of nodes that can be tested with some targeted pattern,
more is the coverage.
• To get more coverage the design needs to be more controllable and observable.
• For the design to be more controllable we need more control points (mux
through which alternate path is provided to propagate pattern).
• For the design to be more observable we need more observe point (A scan-able
flop that observes the value at that node).
• Scan mode is used to test stuck at faults and manufactured devices for delay.
• Scan mode is done using scan chains
• Scan chains are part of scan based designs to propagate the test data.
• By having scan chains, the design can be more controllable and observable.
• Each scan chain inputs the pattern through scan input and outputs the
pattern through scan output.
• Scan chain consists of scan flops where the output of scanflops is directly
connected to scan inputs of the flops.
• Stages of scan mode
• Inputs the pattern through scan input port.
• Scan shift- Scan enable is set to 1. Then inputs the pattern through the scan
input, shifts the pattern through the scan flops and load all the flops with
test pattern.
• Scan capture- Scan enable is set to 0. In one clock cycle the loaded value in
the flops propagates through combinational circuit and reaches the D pin of
the next flop.
• Scan enable is set to 1 and outputs the pattern through scan output port.
• The scan chain length and number of scan chains has to be
properly chosen, as having more scan chain length increases the
pattern propagation time and having more scan chains increases
the number of scan IO ports.

Fig7: Scan chain

• 8. Compile incremental
• Technology mapping of DFT circuit
• Optimization of the design
• 9. Outputs of Synthesis
• netlist
• SDC
• UPF
• ScanDEF- information of scan flops and their connectivity in a scan
chain
 Outputs
• A qualified netlist with scan insertion and good QoR in terms of timing, power,
and area. Other outputs are updated DEF, UPF, and SDC.
1.UPF: The output UPF is the updated version of the input UPF. At the synthesis
stage, it performs logic optimization that introduces new power intents. So, we are
generating UPF with this update after synthesis.
2.DEF: While performing Physical Aware synthesis, we also generate the DEF file,
which contains macro and standard cell placement information. This DEF is
directly used in physical implementation that, avoids placement of the cell from
scratch, hence, we can save run time.
3.SDC: The output SDC is the updated version of the input SDC. At the synthesis
stage, we use constraints provided by the designer. Additionally, we use certain
local constraints to improve the overall QoR of design. Thus, the SDC with this
update is generated after synthesis.
• Checklist
• Check if the RTL and netlist are logically equivalent (LEC/FM).
• Check if SDC and UPF are generated after synthesis and also
check their completeness.
• Check if there are any assign statements.
• Checks related to timing
• Combinational loops(STA)
• Un-clocked registers
• unconstrained IO’s
• IO delay missing
• Un-expandable clocks
• Master slave separation
• multiple clocks
 Netlist quality checks
• Below are certain checks that, should be fulfilled post-synthesis to ensure
netlist qualifications before it is delivered for physical implementation.
• 1. No Clocks:
• In this check, we ensure that all the required clocks reach the sync points.
Some major reasons for getting no clock violation in design are
mentioned below:
• Clock definition missing: This is observed when clock creation is missing
in the clock constraint file.
• RTL connectivity issue/Tie off: This type of no clock is observed when
there is missing connectivity in between modules in the RTL or having
direct tie-offs in the RTL.
• Impact: Ideally, all the registers in the design should be clocked. If
no clock issue is left in the design, then it will report unconstraint
endpoints and can cause optimization issues on such paths.
• Solution: To resolve the above-mentioned no clocks violation, we
need to get the corrected RTL (from the designer) and clock
constraints files with all the required clock definitions.
• Command: check_timing -include {no_clock}
• 2. Unconstraint end-points:
• This is due to the missing IO constraints, clock definitions, or due to
some exceptions at the sequential cells or ports. Possible reasons are
case constant, no arrival path, or false path.
• Impact: If IO constraints are missing in the design, then the
external launch time for the input path or the capture time for the
output path will be missed. It can cause an incomplete timing
check. If the path is expected to be false, it could lead to an
incorrect timing check.
• Solution: To resolve these problems, we need the correct
constraint file (sdc), which defines all the required clocks used in
the design, IO delays on all the required ports, verified false path,
and case constants in design.
• Command: check_timing -include {unconstrained_endpoints}
 3. Timing:
• In this check, the entire design is divided into timing paths. For
each timing path, the delay is calculated and checks violation
based on timing constraints (clock period, clock uncertainty,
and setup time). The major reasons for having timing violations
are- levels of logic, incorrect/missing constraints such as clock
relations, clock exceptions, and incorrect uncertainty.
• Impact: If a huge timing violation is reported at the synthesis,
this violation will be difficult to fix at later stages (PNR/ECO),
which also impacts the power and area.
• Solution: The techniques used to resolve/reduce timing
violations are user-defined path groups with appreciate
weightage, by disabling selectively/entirely multibit banking in
design, bound creation, using timing efforts high or incremental
compilation. If we are performing Physical Aware synthesis, it is
expected to have a good macro placement that improves timing
violations.
• Command: report_timing or report_qor
 4. LEC:
• This is one of the important checks that validate the correctness of the netlist concerning the
RTL.
• It is recommended to perform this check when there is an update in the RTL or netlist.
Generally, in the synthesis LEC, a check is performed between the RTL vs synthesize netlist and
synthesize netlist vs post scan netlist.
• General issues due to which the LEC can fail are as follows:
• CSN Missing: The missing CSN (Connect Supply Net) can lead to LEC failure.
• Isolation cell mapping: When there is an issue with UPF constraint, then there could be a
possibility of having different isolation cells, mapped in between the RTL and synthesize netlist,
that may cause LEC failure.
• Undriven Nets: If we have undriven nets in the RTL, the synthesize tool will tie off these nets
causing LEC failure. This can be resolved by getting the RTL fixed or if the undriven is expected,
then you need to use undriven constraints to pass the LEC.
• Constraint used (formality): set_constants <net_name> <0/1>
• Impact: If the LEC is not clean then the equivalence is not
maintained between the RTL and netlist which can lead to
functionality failure.
• EDA Tool: Formality from Synopsys, conformal from Cadence
 5. Timing loop:
• In the RTL, if in between combo logic, the output is again feed
to the same input of combo logic that forms a logical loop, this
loop is called the timing loop. We can get the timing loops due
to RTL connectivity issues in design that, which can lead to
meta-stable data, thus, we should avoid timing loops while
netlist generation.
• Impact: The path with timing loops will not have endpoints. If
such loops are not broken then the path will not be correctly
timed.
 5. Timing loop:
• Solution: If we are getting timing loops that are expected to
have then in such case, we need to use the constraint to break
such timing loops. If such timing loops are not expected in
design, then we need to get the updated RTL.
• Command: check_timing -include {loops}
 6. Empty module:
• If the RTL module definitions don’t have any logical content
such as wire, inputs, or outputs, then such modules are called
empty modules. This check is performed before compilation.
• By default, empty modules are removed during synthesis. If we
want to preserve this empty module, we need to apply constraint
(set_dont_touch) on that module before compilation.
• Command: check_design
 7. Removed Flop:
• If the register is removed during compilation and optimization,
then such flop is reported as removed flops. If the register is
either unloaded or constant, then by default during compilation
such flip flop is removed from the design.
• If such flip flops are expected in design, then we need to use
certain constraints to preserve this.
• Command:
• report_unloaded_registers
• report_constant_registers
 8. Floating pins and multidriven
pins:
• In the design there might be a possibility that a few of the pins
are not connected to any element present in the design. Such
pins are known as floating pins. While performing optimization,
such floating pins cells might get optimized due to which there
could be a breakdown in logic.
• Multidriven nets are detected when there is more than one input
connected to the same net from different modules. This is not
accepted in design and you need to fix this issue. It requires RTL
correction to resolve this issue.
 9. Latches:
• The latches are not expected in design and during compilation,
the tool gives a warning if the design infers a latch. Below are a
few reasons why a latch is not preferred in design:
1.As latches are level triggers and can change the output at an
active level of the clock.
2.The latch output is stable only at an inactive level of the clock
cycle, due to which the entire clock cycle is not utilized for
timing check.
• Checks related to design
• Floating pins
• multi driven inputs
• un-driven inputs
• un-driven outputs
• normal cells in clock path
• pin direction mismatch
• don’t use cells
THANK YOU