U20CBT303 – COMPUTER ORGANIZATION

AND ARCHITECTURE

UNIT IV MEMORY
ORGANIZATION
 UNIT IV MEMORY ORGANIZATION

Semiconductor memory technologies- Memory

interleaving, concept of hierarchical memory
organization: auxiliary memory –Associate memory
– Virtual memory -cache memory -cache size vs.
block size- mapping functions- replacement
algorithms- write policies
 MEMORY
• Basic functional unit of a computer
• Processor Memory Interaction
• Memory Technologies or Types of Memory Systems – Static RAM, Dynamic RAM
• Memory Interfacing and Addressing - Signals to read from and write to registers
• Memory Interleaving - A smaller memories are combined together to form a large memory,
concurrent access to memory, caches
• Memory Hierarchy Design – Storage vs Speed of Access
• Cache Memory Design – Fast access memory, acts as buffer between RAM and CPU
• Mapping techniques – movement of data blocks from main memory to cache memory -
Direct, Associative, Set Associative mapping
• Techniques for improving cache performance - price/performance ratio, interleaving
 MEMORY
• Used to store the instructions/programs and data in
digital form
• Instructions are brought from the Main Memory
through some Registers to the processor and
executed.
• Operational registers - Memory Address
Register(MAR) and Memory Buffer
Register(MBR) or Memory Data Register(MDR)
 MEMORY
Characteristics of Memory
• Speed
• Size
• Cost
Unit of Memory Size
• 1 bit = the value of 0 or 1
• 8 bits = 1 byte
• 1024 byte =1 kilobyte
• 1024 kilobytes = 1 megabyte
• 1024 megabytes = 1 gigabyte
• 1024 gigabytes = 1 terabyte
• 1024 terabytes = 1 petabyte
 VON NEUMANN ARCHITECT URE
VS
HARVARD ARCHITECTURE

Von Neumann Architecture (stored-program principle)

• Both the instruction and the data are stored in a same memory
• The CPU cannot access instructions and read/write at the same time
• Common bus for data and instruction transfer
Harvard architecture
• The data and instruction are stored in two separate memory(cache memory)
• The CPU can access instructions and read/write at the same time
• Separate buses are used for transferring data and instruction
 BROAD CATEGORIES OR TYPES OF MEMORY

Internal Memory– Register, Cache Memory, Main Memory

• Internal memory is used by CPU to perform the task
• Main memory / RAM (Random Access Memory) – the memory unit that establishes direct communication with the
CPU
External Memory - Magnetic Disk, Removable media (Magnetic tape)
• External memory is used to store bulk information, which includes large software and data.
• Secondary / Auxiliary Memory - The memory units that provide backup storage. Examples: Magnetic disks, and
Magnetic tapes
Memory Hierarchy
• Register
• Cache Memory
• Primary or Main Memory
• Secondary or Magnetic Disk
• Flash memory or Removable media (Magnetic tape)
 INTERNAL MEMORY

• Internal memories are semiconductor memory. Semiconductor

memories are categorized as volatile memory and non-volatile
memory.
• RAM: Random Access Memories are volatile in nature. As soon as
the computer is switched off, the contents of memory are also lost.
• ROM: Read-only memories are nonvolatile in nature. The storage is
permanent, but it is read-only memory. We can not store new
information in ROM.
MAIN MEMORY ADDRESSING
 MEMORY HIERARCHY

Memory ranges
from slow but
high-capacity
secondary /
auxiliary
memory to
relatively faster
main memory.
 MEMORY HIERARCHY

The following image illustrates the components in a typical memory hierarchy.

 REGISTER

• A part of Central Processor Unit, reside inside it.

• The information from main memory is brought to CPU and keep the
information in register.
• Due to space and cost constraints, a limited number of registers are in a
CPU.
• Faster device.
 MAIN MEMORY

• Main Memory is a semiconductor memory.

• It is relatively slower memory.
• The information (whether it is data or program) is first bring from
main memory to CPU.
• CPU can then work with the information available in main memory
only.
 MAGNETIC DISK

• The storage capacity of magnetic disk is very high. Bulk storage

device.
• Semiconductor memories are volatile in nature. It loses its
content once we switch off the computer.
• For permanent storage, we use magnetic disk.
 REMOVABLE MEDIA

• For different applications, we use different data. It may not be

possible to keep all the information on a magnetic disk.
• Which ever data we are not using currently, can be kept in
removable media. Magnetic tape is one kind of removable
medium.
• CD is also a removable media, which is an optical device.
 BUSES

Types of Buses: 
• Data Bus: It carries data among the main memory system, processor, and I/O
devices. 
• Data Address Bus: It carries the address of data from the processor to the
main memory system. 
• Instruction Bus: It carries instructions among the main memory system,
processor, and I/O devices. 
• Instruction Address Bus: It carries the address of instructions from the
processor to the main memory system. 
 MEMORY HIERARCHY

The following image illustrates the components in a typical memory hierarchy.

 MEMORY HIERARCHY - AUXILIARY MEMORY

A Auxiliary memory is the lowest-cost, highest-capacity, and slowest-access

storage in a computer system.
It provides storage for programs and data that are kept for long-term
storage or when not in immediate use.
Examples: Magnetic tapes and magnetic disks.
A magnetic disk is a digital computer memory that uses a magnetization
process to write, rewrite and access data. Examples: Hard drives, zip disks, and
floppy disks.
Magnetic tape is a storage medium that allows for data archiving, collection,
and backup for different kinds of data.
A Auxiliary memory access time is generally 1000 times that of the main
memory, hence it is at the bottom of the hierarchy.
 MEMORY HIERARCHY - MAIN MEMORY

The main memory is also known as Random Access Memory (RAM).

This memory unit communicates directly with the CPU and with auxiliary memory
devices through an I/O processor.
The programs that are not currently required in the main memory are transferred into
auxiliary memory to provide space for currently used programs and data
The main memory occupies the central position because it is equipped to communicate
directly with the CPU and with auxiliary memory devices through Input/output
processor (I/O).
 MAIN MEMORY
• The main memory / Primary memory holds only those data and instructions on which computer is
currently working.
• The main memory unit of computer is basically consists of two kinds of memory:
RAM : Random access memory; which is volatile in nature.
ROM: Read only memory; which is non-volatile.
• The permanent information are kept in ROM and the user space is basically in RAM.
• The smallest unit of information is known as bit (binary digit), and in one memory cell we can store one
bit of information. 8 bit together is termed as a byte.
• It has limited capacity and data is lost when power is switched off.
• It is generally made up of semiconductor device. These memories are not as fast as registers.
• The data and instruction required to be processed reside in main memory.
• It is divided into two sub categories RAM and ROM.
 MEMORY HIERARCHY - I/O PROCESSOR

The primary function of an I/O Processor is to manage the data transfers between
auxiliary memories and the main memory.
 MEMORY HIERARCHY - CACHE MEMORY

The data or contents of the main memory that are used frequently by CPU are stored in
the cache memory so that the processor can easily access that data in a shorter time.
Whenever the CPU requires accessing memory, it first checks the required data into the
cache memory. If the data is found in the cache memory, it is read from the fast
memory. Otherwise, the CPU moves onto the main memory for the required data
The cache memory is used to store program data that is currently being executed in the
CPU.
 MAIN MEMORY

The main memory acts as the central storage unit in a computer system. It is a relatively
large and fast memory which is used to store programs and data during the run time
operations.
The primary technology used for the main memory is based on semiconductor
integrated circuits. The integrated circuits for the main memory are classified into two
major units.
1. RAM (Random Access Memory) integrated circuit chips

2. ROM (Read Only Memory) integrated circuit chips

 MEMORY MANAGEMENT

• In the stored principle concept, all the information is kept in the main
memory, and the CPU interacts with the main memory only.
• Everything cannot be implemented in hardware, because, the cost
of the system will be very high.
• Therefore some of the tasks are performed by the software program.
The collection of such software programs that assigns storage
space in memory and controls input and output functions are known
as operating systems.
• The program currently being executed by the CPU is loaded into
the user part of the memory is known as the user program.
 MEMORY MANAGEMENT

• The main memory of a computer is divided into two parts.

1. Operating system.
2. User program
• In a uni-programming system, the program currently being executed
is loaded into the user part of the memory.
• In a multiprogramming system, the user part of memory is
subdivided to accommodate multiple processes. The task of the
subdivision is carried out dynamically by the operating system and is
known as memory management.
 MEMORY MANAGEMENT

• In a uniprogramming system, only

one program is in execution.
• After completion of one program,
another program may start.
• In general, most of the programs
involve I/O operations.
• It must take input from some input
device and place the result in some
output device.
 MAIN MEMORY

RAM INTEGRATED CIRCUIT CHIPS

The RAM integrated circuit chips are further classified into two possible
operating modes, static and dynamic.
The primary compositions of a Static RAM (SRAM) are flip-flops that store
binary information.
The nature of the stored information is volatile, i.e. it remains valid as long as
power is applied to the system.
The static RAM is easy to use and takes less time performing read and write
operations as compared to dynamic RAM.
 MAIN MEMORY

RAM INTEGRATED CIRCUIT CHIPS

The dynamic RAM (DRAM) exhibits the binary information in the form of electric
charges that are applied to capacitors. The capacitors are integrated inside the chip by
MOS transistors. The dynamic RAM consumes less power and provides a large
storage capacity in a single memory chip.
RAM chips are available in a variety of sizes and are used as per the system
requirement. The following block diagram demonstrates the chip interconnection in a
128 * 8 RAM chip.
 MAIN MEMORY

RAM INTEGRATED CIRCUIT CHIPS

Chip select is the

active low signal
CS-0, activates I/O
lines to transfer data
 MAIN MEMORY

RAM INTEGRATED CIRCUIT CHIPS

A 128 * 8 RAM chip has a memory capacity of 128 words of eight bits (one byte) per
word. This requires a 7-bit address and an 8-bit bidirectional data bus.
The 8-bit bidirectional data bus allows the transfer of data either from memory to CPU
during a read operation or from CPU to memory during a write operation.
The read and write inputs specify the memory operation, and the two chip select (CS)
control inputs are for enabling the chip only when the microprocessor selects it.
 MAIN MEMORY

RAM INTEGRATED CIRCUIT CHIPS

The bidirectional data bus is constructed using three-state buffers.

The output generated by three-state buffers can be placed in one of the three possible
states which include a signal equivalent to logic 1, a signal equal to logic 0, or a high-
impedance state
High impedance implies that the output is disconnected, leaving the signal open, to
be driven by another device
When the control input is 0, the output is disabled and the gate will be in a high
impedance state
 MAIN MEMORY

RAM INTEGRATED CIRCUIT CHIPS

The following function table specifies the operations of a 128 * 8 RAM chip

From the functional table, we can conclude that the unit is in operation only when CS1 = 1 and CS2 = 0. The bar on
top of the second select variable indicates that this input is enabled when it is equal to 0.
 MAIN MEMORY

ROM INTEGRATED CIRCUIT

The primary component of the main memory is RAM integrated circuit chips, but a
portion of memory may be constructed with ROM chips.
A ROM memory is used for keeping programs and data that are permanently resident in
the computer.
Apart from the permanent storage of data, the ROM portion of main memory is needed
for storing an initial program called a bootstrap loader. The primary function of
the bootstrap loader program is to start the computer software operating when power
is turned on.
 MAIN MEMORY

ROM INTEGRATED CIRCUIT

ROM chips are also available in a variety of sizes and are also used as per the system
requirement. The following block diagram demonstrates the chip interconnection in a
512 * 8 ROM chip
 MAIN MEMORY

ROM INTEGRATED CIRCUIT

A ROM chip has a similar organization as a RAM chip. However, a ROM can only
perform read operation; the data bus can only operate in an output mode.
The 9-bit address lines in the ROM chip specify any one of the 512 bytes stored in it.
The value for chip select 1 and chip select 2 must be 1 and 0 for the unit to operate.
Otherwise, the data bus is said to be in a high-impedance state.
Types of ROM:
• ROM
• PROM
• EPROM
• EEPROM
Several types of ROM are available:
• PROM: Programmable Read-Only Memory; it can be programmed once as per user
requirements.
• EPROM: Erasable Programmable Read-Only Memory; the contents of the memory
can be erased and store
• New data into the memory. In this case, we have to erase the whole information.
• EEPROM: Electrically Erasable Programmable Read-Only Memory; in this type of
memory the contents of a particular location can be changed without affecting the
contents of another location.
 ROM VS RAM

There is one major difference between a ROM and a RAM chip:

• A ROM chip is non-volatile storage and does not require a constant source of power to retain
information stored on it. When power is lost or turned off, a ROM chip will keep the information
stored on it. So for permanent storage, ROM is used.
• In contrast, a RAM chip is volatile and requires a constant source of power to retain information.
When power is lost or turned off, a RAM chip will lose the information stored on it.
• A ROM chip is used primarily in the start-up process of a computer, whereas a RAM chip is used
in the normal operations of a computer after starting up and loading the operating system.
• Writing data to a ROM chip is a slow process, whereas writing data to a RAM chip is a faster
process
• A RAM chip can store multiple gigabytes (GB) of data, up to 16 GB or more per chip; A ROM
chip typically stores only several megabytes (MB) of data, up to 4 MB or more per chip
 A D VA N TA G E S O F M A I N M E M O RY

These are semiconductor memories

• It is the working memory of the computer
• Faster than secondary memories
• Cheaper than Cache memory
Disadvantages of Main Memory:
• Volatile when the power goes off
• High cost as transistors are used
• Usually size is less than secondary memory
 S EC O N D ARY S TO R A G E D EV I C E S ( A U X IL I A RY ME MO RY D EV I C ES )

The secondary storage devices which are built into the computer or
connected to the computer are known as secondary memory / external
memory / auxiliary storage.
The secondary memory is accessed indirectly via input/output operations.
It is non-volatile, so permanently stores the data even when the computer
is turned off or until this data is overwritten or deleted.
The CPU can't directly access the secondary memory. First, the secondary
memory data is transferred to primary memory then the CPU can access it.
 AUXILIARY MEMORY DEVICES

Some of the secondary memory or storage devices are:

•Hard Disk
•Pen drive
•SD Card
•Solid-State Drive
•Compact Disk (CD)
•DVD
 AUXILIARY MEMORY DEVICES

Hard Disk / Hard Drive

It is a rigid magnetic disc that is used to store data
permanently
It is located within a drive unit on the computer's motherboard
and comprises one or more platters packed in an air-sealed
casing.
It includes the operating system, installed software, and the
user's files and programs, including pictures, music, videos, text

documents, etc.
 AUXILIARY MEMORY DEVICES

 Pen drive
Pen drive is a compact secondary storage device.
It is also known as a USB flash drive, thumb drive or
a jump drive.
It connects to a computer via a USB port.
It is used to store and transfer data between
computers.
It ranges from 2 GB to 128 GB
 AUXILIARY MEMORY DEVICES

SD Card:
SD Card stands for Secure Digital Card.
It is most often used in portable and mobile devices such as smartphones and
digital cameras.
You can remove it from your device and see the things stored in it using a
computer with a card reader.
There are many memory chips inside the SD card that store the data; it does
not have moving parts.
SD cards are not created with equal speed, physical size, and capacity.
Example - standard SD cards, mini SD cards, and micro SD cards.
 SECONDARY STORAGE DEVICES

Compact Disk (CD):

Compact Disk is a portable secondary storage
device in the shape of a round medium disk.
It is made of polycarbonate plastic. The concept of CD
was co-developed by Philips and Sony in 1982.
The first CD was created on 17 August 1982 at the
workshop of Philips in Germany.
In the beginning, it was used for storing and playing
sound recordings, later it was used for various purposes
such as for storing documents, audio files, videos, and
other data like software programs in a CD.
 S E C O N D A RY M E M O RY

• This type of memory is also known as external memory or non-volatile. It is slower than the main memory.
• These are used for storing data/Information permanently. CPU directly does not access these memories instead they
are accessed via input-output routines.
• Contents of secondary memories are first transferred to the main memory, and then the CPU can access it. For
example disk, CD-ROM, DVD, etc.
Advantages of Secondary Memory
• These are magnetic and optical memories
• It is known as backup memory.
• It is non-volatile memory.
• Data is permanently stored even if power is switched off.
• It is used for storage of data in a computer.
Disadvantages of Secondary Memory
• Computer doesn’t deal with secondary memory at the beginning of execution.
• Slower than primary memories.
 AUXILIARY MEMORY DEVICES

DVD:
DVD is short for digital versatile disc or digital video disc. It is
a type of optical media used for storing optical data. Although it
has the same size as a CD, its storage capacity is much more than
a CD. So, it is widely used for storing and viewing movies and to
distribute software programs as they are too large to fit on a CD.
DVD was co-developed by Sony, Panasonic, Philips, and
Toshiba in 1995..
ASSOCIATIVE MEMORY
 ASSOCIATIVE MEMORY

•An associative memory can be considered as a memory unit whose stored data can be
identified for access by the content of the data itself rather than by an address or
memory location.
Associative memory is often referred to as Content Addressable Memory (CAM).
When a write operation is performed on associative memory, no address or memory
location is given to the word. The memory itself is capable of finding an empty unused
location to store the word.
On the other hand, when the word is to be read from an associative memory, the content of
the word, or part of the word, is specified. The words which match the specified content are
located by the memory and are marked for reading.
 ASSOCIATIVE MEMORY

The following diagram shows the block representation of an Associative memory.

 ASSOCIATIVE MEMORY

•From the block diagram, we can say that an associative memory consists of a memory
array and logic for 'm' words with 'n' bits per word.
•The functional registers like the argument register A and key register K each have n bits,
one for each bit of a word. The match register M consists of m bits, one for each memory
word.
•The words which are kept in the memory are compared in parallel with the content of the
argument register.

.
 ASSOCIATIVE MEMORY

•The key register (K) provides a mask for choosing a particular field or
key in the argument word.
•If the key register contains a binary value of all 1's, then the entire
argument is compared with each memory word.
•Otherwise, only those bits in the argument that have 1's in their
corresponding position of the key register are compared.
•Thus, the key provides a mask for identifying a piece of information that
specifies how the reference to memory is made.
VIRTUAL MEMORY
 V I RT U A L M E M O RY

• Virtual memory is a technique that uses main memory as a “cache” for

secondary storage.

• Two major motivations for virtual memory:

• to allow efficient and safe sharing of memory among multiple programs, and

• to remove the programming burdens of a small, limited amount of main memory.

 VIRTUAL MEMORY

•Virtual memory is a section of volatile memory (primary memory) created temporarily

on the storage drive. It is created when a computer is running many processes at once
and RAM is running low.
•Virtual memory is a feature of an operating system that enables a computer to be able to
compensate shortages of physical memory by transferring pages of data from random
access memory to disk storage.
•This process is done temporarily and is designed to work as a combination of RAM and
space on the hard disk.
 VIRTUAL MEMORY

•This means that when RAM runs low, virtual memory can move data from it to a space
called a paging file. This process allows for RAM to be freed up so that a computer can
complete the task.
•Occasionally a user might be shown a message that says the virtual memory is running low,
this means that either more RAM needs to be added, or the size of the paging file needs to
be increased.
.
 VIRTUAL MEMORY
.
•Virtual Memory is a storage scheme that provides user an illusion of having a very big
main memory.
•This is done by treating a part of secondary memory as the main memory.
•In this scheme, User can load the bigger size processes than the available main memory by
having the illusion that the memory is available to load the process. Instead of loading one
big process in the main memory, the Operating System loads the different parts of more
than one process in the main memory.
•By doing this, the degree of multiprogramming will be increased and therefore, the CPU
utilization will also be increased.
 VIRTUAL MEMORY

(Pages)
 HOW VIRTUAL MEMORY WORKS?

•In modern word, virtual memory has become quite common these days. In this scheme,
whenever some pages needs to be loaded in the main memory for the execution and the
memory is not available for those many pages, then in that case, instead of stopping the
pages from entering in the main memory, the OS search for the RAM area that are least
used in the recent times or that are not referenced and copy that into the secondary memory
to make the space for the new pages in the main memory.
•Since all this procedure happens automatically, therefore it makes the computer feel like it
is having the unlimited RAM.
.
 VIRTUAL MEMORY

Advantages of Virtual Memory

•The degree of Multiprogramming will be increased.
•User can run large applications with less real RAM.

•There is no need to buy more memory RAMs.

.
 VIRTUAL MEMORY

Disadvantages of Virtual Memory

•The system becomes slower since swapping takes time.
•It takes more time in switching between applications.

•The user will have lesser hard disk space for its use.

.
 VIRTUAL ADDRESSES

.
•A virtual address is a binary number in virtual memory that enables a process to
use a location in primary storage (main memory) independently 
.
•The address of a program to access virtual memory is called virtual address.

A virtual address consists of two parts;

1) the page and
2) an offset into that page.
 VIRTUAL ADDRESSES

PAGE
.
• A page, memory page, or virtual page is a fixed-length contiguous block of
virtual memory, described by a single entry in the page table.
.
•It is the smallest unit of data for memory management in a virtual memory
operating system.
•secondary memory is divided into equal size partitions called as pages.
• Since the entire possible address space is divided up into regular sized pages,
every possible address resides within a page. The page component of the virtual
address acts as an index into the page table.
 VIRTUAL ADDRESSES

PAGE
.
• Since the page is the smallest unit of memory allocation within the system there
is a trade-off between making pages very small, and thus having very many pages
.
for the operating-system to manage, and making pages larger but potentially
wasting memory
 VIRTUAL ADDRESSES

OFFSET INTO THAT PAGE

.
 Offset is an integer or location indicating the distance (displacement) between
the beginning of the object and a given element or point, presumably within the
.same object.

For example, in A as an array of characters containing "abcdef", the fourth

element containing the character 'd' has an offset of three from the start of A
 VIRTUAL ADDRESSES

OFFSET INTO THAT PAGE

.
• The last bits of the virtual address are called the offset which is the location
difference between the byte address you want and the start of the page.
. You require enough bits in the offset to be able to get to any byte in the page.
• For a 4K page you require (4K == (4 * 1024) == 4096 == 212 ==) 12 bits of
offset. Remember that the smallest amount of memory that the operating
system or hardware deals with is a page, so each of these 4096 bytes reside
within a single page and are dealt with as "one".
 VIRTUAL ADDRESSES

OFFSET INTO THAT PAGE

.

.
 VIRTUAL ADDRESS TRANSLATION

 Virtual address translation refers to the process of finding out which physical
.
page maps to which virtual page.
When translating a virtual-address to a physical-address we only deal with
.the page number .

The essence of the procedure is to take the page number of the given address and
look it up in the page-table to find a pointer to a physical address, to which the
offset from the virtual address is added, giving the actual location in system
memory.
 VIRTUAL ADDRESS TRANSLATION

Since the page-tables are under the control of the operating system, if the
.
virtual-address doesn't exist in the page-table then the operating-system knows the
process is trying to access memory that has not been allocated to it and the access
.will not be allowed.
Virtual Address Translation method
 VIRTUAL ADDRESS TRANSLATION

.
 VIRTUAL ADDRESS TRANSLATION

.
CACHE MEMORY
 CACHE MEMORY

• Cache memory is a storage device placed in between CPU and main

memory to increase the efficiency.
• These are semiconductor memories, metal–oxide–semiconductor (MOS)
memory.
• Fast memory device, which is faster than the main memory.
• Small size memory due to higher cost and some constraints of the CPU.
• It can not replace the whole main memory by faster memory.
• The most recently used information is kept in the cache memory.
• Information is brought from the main memory and placed in the CPU
with internal cache memory.
 CACHE MEMORY
• A number of instructions are executed repeatedly, such as simple loops, nested
loops, or a few procedures, that repeatedly call each other.
• It is observed that many instructions in each of a few localized areas of the
program are repeatedly executed, while the remainder of the program is accessed
relatively less. This phenomenon is referred to as locality of reference.
• The active segments of a program in a fast memory, then the total execution time
can be significantly reduced.
• It is 5 to 10 time faster than the main memory.
• Reduces the frequent data transfer between main memory and cache memory.
 CACHE MEMORY

The advantages of cache memory are as follows:

 Cache memory is faster than main memory.
 It consumes less access time as compared to main memory.
 It stores the program that can be executed within a short period of time.
 It stores data for temporary use.
The disadvantages of cache memory are as follows:
 Cache memory has limited capacity.
 It is very expensive.
 CACHE MEMORY

The cache is the fastest component in the memory hierarchy and approaches the speed of CPU
components.
 CACHE MEMORY

•The data or contents of the main memory that are used frequently by CPU are stored in
the cache memory so that the processor can easily access that data in a shorter time.
•Whenever the CPU needs to access memory, it first checks the cache memory. If the data is
not found in cache memory, then the CPU moves into the main memory.
•Cache memory is placed between the CPU and the main memory. The block diagram for a
cache memory can be represented in previous slide
.
 CACHE MEMORY

The basic operation of a cache memory is as follows:

•When the CPU needs to access memory, the cache is examined. If the word is found in the
cache, it is read from the fast memory.
•If the word addressed by the CPU is not found in the cache, the main memory is accessed
to read the word.
•A block of words one just accessed is then transferred from main memory to cache
memory. The block size may vary from one word (the one just accessed) to about 16 words
adjacent to the one just accessed.
•The performance of the cache memory is frequently measured in terms of a quantity
called hit ratio.
 CACHE MEMORY

•When the CPU refers to memory and finds the word in the cache, it is said to
produce a hit.
• If the word is not found in the cache, it is in the main memory and it counts
as a miss.
• The ratio of the number of hits divided by the total CPU references to
memory (hits plus misses) is the hit ratio.
 DIRECT-MAPPED CACHE

•Direct-mapped cache is a cache structure in which each memory location is

mapped to exactly one location in the cache.

•For example, almost all direct-mapped caches use this mapping to find a block,
(Block address) modulo (Number of blocks in the cache)
 (BLOCK ADDRESS) MODULO (NUMBER
OF BLOCKS IN THE CACHE)

• Example
• Consider a cache with 64 blocks and a block size of 16 bytes. To what block number does byte address
1200 map?
 T H E S T E P S TO B E TA K E N I N A N I N S T R U C T I O N C A C H E
MISS

• Send the original PC value to the memory.

• Instruct main memory to perform a read and wait for the memory to
complete its access.
 D I F F E R E N T I AT E P H Y S I C A L A D D R E S S F R O M L O G I C A L
ADDRESS

• Physical address is an address in main memory.

• Logical address (or) virtual address is the CPU generated addresses
that corresponds to a location in virtual space and is translated by
address mapping to a physical address when memory is accessed.
 PA G E FA U LT

• Page fault is an event that occurs when an accessed page is

not present in main memory.
 ROTATIONAL LATENCY

•Rotational latency, also called rotational delay, is the time

required for the desired sector of a disk to rotate under the
read/write head, usually assumed to be half the rotation time.
 CACHE MEMORY - MAPPING FUNCTIONS

• The mapping functions are used to map a particular block of main memory to a particular block of
cache.
• This mapping function is used to transfer the block from main memory to cache memory.
Three different mapping functions are available:
• Direct mapping:
• A particular block of main memory can be brought to a particular block of cache memory. So, it is not flexible.
• Associative mapping:
• In this mapping function, any block of Main memory can potentially reside in any cache block position.
• This is much more flexible mapping method.
• Block-set-associative mapping:
• In this method, blocks of cache are grouped into sets, and the mapping allows a block of main memory to
reside in any block of a specific set. From the flexibility point of view, it is in between to the other
two methods.
Why we need mapping ?
• Consider a cache of 4096 (4K) words with a block size of 32 words. Therefore, the cache is organized as 128
blocks.
• For 4K words, required address lines are 12 bits. To select one of the block out of 128 blocks, we need 7 bits
of
• address lines and to select one word out of 32 words, we need 5 bits of address lines.
• So the total 12 bits of address is divided for two groups, lower 5 bits are used to select a word within a block,
and higher 7 bits of address are used to select any block of cache memory.
• Let us consider a main memory system consisting 64K words. The size of address bus is 16 bits. Since the
block size of cache is 32 words, so the main memory is also organized as block size of 32 words. Therefore,
the total number of blocks in main memory is 2048 (2K x 32 words = 64K words).
• To identify any one block of 2K blocks, we need 11 address lines.
• Out of 16 address lines of main memory, lower 5 bits are used to select a word within a block and higher 11
bits are used to select a block out of 2048 blocks.
• Number of blocks in cache memory is 128 and number of blocks in main memory is 2048, so at any instant of
time only 128 blocks out of 2048 blocks can reside in cache menory.
• Therefore, we need mapping function to put a particular block of main memory into appropriate block of cache
memory.
 DIRECT MAPPING TECHNIQUE

• The simplest way of associating main memory blocks with cache block is the direct mapping technique.
• In this technique, block k of main memory maps into block k modulo m of the cache, where m is the total number of blocks in cache. ]
• In this example, the value of m is 128. In direct mapping technique, one particular block of main memory can be transferred to a particular
block of cache which is derived by the modulo function.
• Since more than one main memory block is mapped onto a given cache block position, contention may arise for that position. This situation
may occurs even when the cache is not full.
• Contention is resolved by allowing the new block to overwrite the currently resident block. So the replacement algorithm is trivial.
The detail operation of direct mapping technique is as follows:
• The main memory address is divided into three fields. The field size depends on the memory capacity and the block
• size of cache.
• In this example, the lower 5 bits of address is used to identify a word within a block.
• Next 7 bits are used to select a block out of 128 blocks (which is the capacity of the cache).
• The remaining 4 bits are used as a TAG to identify the proper block of main memory that is mapped to cache.
• When a new block is first brought into the cache, the high order 4 bits of the main memory address are stored in four TAG bits associated
with its location in the cache.
• When the CPU generates a memory request, the 7-bit block address determines the corresponding cache block.
• The TAG field of that block is compared to the TAG field of the address.
• If they match, the desired word specified by the low-order 5 bits of the address is in that block of the cache.
 DIRECT-MAPPING CACHE

If there is no match, the required word

must be accessed from the main
memory, that is, the contents of that
block of the cache is replaced by the
new block that is specified by the new
address generated by the CPU and
correspondingly the TAG bit will also be
changed by the high order 4 bits of the
address. The whole arrangement for
direct mapping technique is shown in the
figure.
 A S S O C I AT E D M A P P I N G T E C H N I Q U E :

• In the associative mapping technique, the main memory block can potentially reside in any cache block
position.
• In this case, the main memory address is divided into two groups, low-order bits identifies the location of a
word within a block and high-order bits identifies the block.
• In the example here, 11 bits are required to identify a main memory block when it is resident in the cache ,
high-order 11 bits are used as TAG bits and low-order 5 bits are used to identify a word within a block.
• The TAG bits of an address received from the CPU must be compared to the TAG bits of each block of the
cache to see if the desired block is present.
• In the associative mapping, any block of main memory can go to any block of cache, so it has got the
complete flexibility and we have to use proper replacement policy to replace a block from cache if the
currently accessed block of main memory is not present in cache.
• It might not be practical to use this complete flexibility of associative mapping technique due to searching
overhead, because the TAG field of main memory address has to be compared with the TAG field of all the
cache block.
• In this example, there are 128 blocks in cache and the size of TAG is 11 bits. The whole arrangement of
Associative Mapping Technique is shown in the figure
ASSOCIATED-MAPPING CACHE
 B L O C K - S E T- A S S O C I AT I V E M A P P I N G T E C H N I Q U E

• This mapping technique is intermediate to the above two techniques. Blocks of the cache are grouped into
sets, and the mapping allows a block of main memory to reside in any block of a specific set.
• Therefore, the flexibity of associative mapping is reduced from full freedom to a set of specific blocks. This
also reduces the searching overhead, because the search is restricted to number of sets, instead of number
of blocks. Also the contention problem of the direct mapping is eased by having a few choices for block
replacement.
• Consider the same cache memory and main memory organization of the previous example. Organize the
cache with 4 blocks in each set. The TAG field of associative mapping technique is divided into two groups,
one is termed as SET bit and the second one is termed as TAG bit.
• Since each set contains 4 blocks, total number of set is 32. The main memory address is grouped into three
parts: low-order 5 bits are used to identifies a word within a block. Since there are total 32 sets present, next
5 bits are used to identify the set. High-order 6 bits are used as TAG bits.
 BLOCK-SET-ASSOCIATIVE MAPPING
TECHNIQUE

• The 5-bit set field of the address determines which set of the cache might contain the desired
block. This is similar to direct mapping technique, in case of direct mapping, it looks for block, but
in case of block-set-associative mapping, it looks for set.
• The TAG field of the address must then be compared with the TAGs of the four blocks of that set.
If a match occurs, then the block is present in the cache; otherwise the block containing the
addressed word must be brought to the cache. This block will potentially come to the
cooresponding set only.
• Since, there are four blocks in the set, we have to choose appropriately which block to be
replaced if all the blocks are occupied. Since the search is restricted to four block only, so the
searching complexity is reduced. The whole arrangement of block-set-associative mapping
technique is shown in the figure.
 BLOCK- SET-ASSOCIATIVE MAPPING TECHNIQUE

• It is clear that if we increase the number

of blocks per set, then the number of bits
in SET field is reduced.
• Due to the increase of blocks per set,
complexity of search is also increased.
• The extreme condition of 128 blocks
• per set requires no set bits and
corresponds to the fully associative
mapping technique with 11 TAG
• bits. The other extreme of one block per
set is the direct mapping method.
 O P E R AT I O N O F C A C H E M E M O RY

• The memory control circuitry is designed to take advantage of the property of locality of reference.
• Some assumptions are made while designing the memory control circuitry:
1. The CPU does not need to know explicitly about the existence of the cache.
2. The CPU simply makes Read and Write request. The nature of these two operations are same whether cache is
present or not.
3. The address generated by the CPU always refer to location of main memory.
4. The memory access control circuitry determines whether or not the requested word currently exists in the cache.
• When a Read request is received from the CPU, the contents of a block of memory words containing the
location specified are transferred into the cache.
• When any of the locations in this block is referenced by the program, its contents are read directly from the
cache.
• The cache memory can store a number of such blocks at any given time.
• The correspondence between the Main Memory Blocks and those in the cache is specified by means of a
mapping function.
• When the cache is full and a memory word is referenced that is not in the cache, a decision must be made as to
which block should be removed from the cache to create space to bring the new block to the cache that
contains the referenced word.
• Replacement algorithms are used to make the proper selection of block that must be replaced by the new
one.
• When a write request is received from the CPU, there are two ways that the system can proceed.
• In the first case, the cache location and the main memory location are updated simultaneously. This is called the
store through method or write through method.
• The alternative is to update the cache location only. During replacement time, the cache block will be written
back to the main memory. If there is no new write operation in the cache block, it is not required to write back
the cache block in the main memory. This information can be kept with the help of an associated bit. This bit it
set while there is a write operation in the cache block.
• During replacement, it checks this bit, if it is set, then write back the cache block in main memory otherwise not.
This bit is known as dirty bit. If the bit gets dirty (set to one), writting to main memory is required.
• This write through method is simpler, but it results in unnecessary write operations in the main memory when a
given cache word is updated a number of times during its cache residency period.
• Consider the case where the addressed word is not in the cache and the operation is a read. First the block of
the words is brought to the cache and then the requested word is forwarded to the CPU. But it can be forwarded
to the CPU as soon as it is available to the cache, instead of whole block to be loaded into the cache. This is
called load through, and there is some scope to save time while using load through policy.
• During a write operation, if the address word is not in the cache, the
information is written directly into the main memory.
• A write operation normally refers to the location of data areas and the
property of locality of reference is not as pronounced in accessing
data when write operation is involved.
• Therefore, it is not advantageous to bring the data block to the cache
when there a write operation, and the addressed word is not present
in cache.
CACHE MEMORY MAPPING
 CACHE MEMORY MAPPING

•Main memory is divided into equal size partitions called

as blocks or frames.
•Cache memory is divided into partitions having same size as that of
blocks called as lines.
•During cache mapping, block of main memory is simply copied to
the cache
 CACHE MAPPING TECHNIQUES
.
 CACHE MAPPING TECHNIQUES

https://www.gatevidyalay.com/cache-mapping-cache-mapping-techniques/

https://www.geeksforgeeks.org/cache-memory-in-computer-organization/
https://www.studytonight.com/computer-architecture/mapping-and-virtual-memory
 CACHE MEMORY MAPPING

In direct mapping,
•A particular block of main memory can map only to a particular line of the cache.
•maps each block of main memory into only one possible cache line. or
In Direct mapping, assign each memory block to a specific line in the cache.
•The line number of cache to which a particular block can map is given by

Cache line number

= ( Main Memory Block Address ) Modulo (Number of lines in Cache)

i = j modulo m
where i=cache line number j= main memory block number m=number of lines in the
cache
 CACHE MEMORY MAPPING

.
 CACHE MEMORY MAPPING

In fully associative mapping,

•A block of main memory can map to any line of the cache that is freely available at that
moment.
•This makes fully associative mapping more flexible than direct mapping.

.
CACHE MEMORY MAPPING
 CACHE MEMORY MAPPING

In fully associative mapping,

•Here, (in the diagram) , All the lines of cache are freely available.
•Thus, any block of main memory can map to any line of the cache.
•Had all the cache lines been occupied, then one of the existing
blocks will have to be replaced.
 CACHE MEMORY MAPPING

K-way Set Associative Mapping-

•In k-way set associative mapping,
•Cache lines are grouped into sets where each set contains k number of lines.

•A particular block of main memory can map to only one particular set of the cache.
•However, within that set, the memory block can map any cache line that is freely available.

•The set of the cache to which a particular block of the main memory can map is given by
 CACHE MEMORY MAPPING

.
 REPLACEMENT ALGORITHMS

• When a new block must be brought into the cache and all the positions that it may occupy are full, a decision
must be made as to which of the old blocks is to be overwritten.
• In general, a policy is required to keep the block in cache when they are likely to be referenced in near future.
• However, it is not easy to determine directly which of the block in the cache are about to be referenced. The
property of locality of reference gives some clue to design good replacement policy.
Least Recently Used (LRU) Replacement policy:
• Since program usually stay in localized areas for reasonable periods of time, it can be assumed that there is
a high probability that blocks which have been referenced recently will also be referenced in the near future.
Therefore, when a block is to be overwritten, it is a good decision to overwrite the one that has gone for
longest time without being referenced.
• This is defined as the least recently used (LRU) block. Keeping track of LRU block must be done as
computation proceeds.
• Consider a specific example of a four-block set. It is required to track the LRU block of this four-block set. A 2-
bit counter may be used for each block. When a hit occurs, that is, when a read request is received for a word
that is in the cache, the counter of the block that is referenced is set to 0. All counters which values originally
lower than the referenced one are incremented by 1 and all other counters remain unchanged.
 REPLACEMENT ALGORITHMS

• When a miss occurs, that is, when a read request is received for a word and
the word is not present in the cache, we have to bring the block to cache.
There are two possibilities in case of a miss:
• If the set is not full, the counter associated with the new block loaded from the
main memory is set to 0, and the values of all other counters are incremented
by 1.
• If the set is full and a miss occurs, the block with the counter value 3 is
removed , and the new block is put in its palce. The counter value is set to zero.
The other three block counters are incremented by 1.
• It is easy to verify that the counter values of occupied blocks are always
distinct. Also it is trivial that highest counter value indicates least recently used
block.
 REPLACEMENT ALGORITHMS

First In First Out (FIFO) replacement policy:

• A reasonable rule may be to remove the oldest from a full set when a new block must be
brought in.
• While using this technique, no updation is required when a hit occurs.
• When a miss occurs and the set is not full, the new block is put into an empty block and the
counter values of the occupied block will be increment by one.
• When a miss occurs and the set is full, the block with highest counter value is replaced by new
block and counter is set to 0, counter value of all other blocks of that set is incremented by 1.
The overhead of the policy is less, since no updation is required during hit.
Random replacement policy:
• The simplest algorithm is to choose the block to be overwritten at random. Interestingly enough,
this simple algorithm has been found to be very effective in practice.
 CACHE MEMORY REPLACEMENT ALGORITHMS

•A cache algorithm is a detailed list of instructions that directs which items should be

discarded in a computing device's cache of information. 
Examples of cache algorithms include:
Least Frequently Used (LFU)
Least Recently Used (LRU)
Adaptive Replacement Cache (ARC)
Most Recently Used (MRU)
 CACHE MEMORY ALGORITHMS

Least Frequently Used (LFU)

•. This cache algorithm uses a counter to keep track of how often an entry is
accessed. With the LFU cache algorithm, the entry with the lowest count is
removed first.
•This method isn't used that often, as it does not account for an item that had an
initially high access rate and then was not accessed for a long time.
 CACHE MEMORY ALGORITHMS

Least Recently Used (LRU).

•This cache algorithm keeps recently used items near the top of cache. Whenever a new
item is accessed, the LRU places it at the top of the cache.
•When the cache limit has been reached, items that have been accessed less recently will be
removed starting from the bottom of the cache.
 CACHE MEMORY ALGORITHMS

Adaptive Replacement Cache (ARC):

•This Developed at the IBM Almaden Research Center, this cache algorithm
keeps track of both LFU and LRU, as well as evicted cache entries to get the
best use out of the available cache.
Most Recently Used (MRU): 
This cache algorithm removes the most recently used items first. A MRU
algorithm is good in situations in which the older an item is, the more likely it
is to be accessed.
 CACHE COHERENCE PROTOCOLS .

•In multiprocessor system where many processes needs a copy of same memory block, the
maintenance of consistency among these copies raises a raises a problem referred to
as Cache Coherence Problem.
This occurs mainly due to these causes:-
Sharing of writable data.
Process migration.
Inconsistency due to I/O.
CACHE COHERENCE PROTOCOLS .
CACHE COHERENCE PROTOCOLS .
CACHE COHERENCE PROTOCOLS .
 MAIN MEMORY SIZE / ADDRESSING
SCHEME

• The maximum size of main memory that can be used in any computer is
determined by the addressing scheme.
• A computer that generates 16-bit address is capable of addressing upto 216
which is equal to 64K memory location. Similarly,
• for 32 bit addresses, the total capacity will be 232 which is equal to 4G memory
location.
• In some computer, the smallest addressable unit of information is a memory
word and the machine is called word addressable.
• In some computer, individual address is assigned for each
byte of information, and it is called byte-addressable
computer.
• In this computer, one memory word contains one or more
memory bytes which can be addressed individually.
• A byte addressable 32-bit computer, each memory word
contains 4 bytes. A possible way of address assignment is
shown in figure. The address of a word is always integer
multiple of 4.
• The main memory is usually designed to store and retrieve
data in word length quantities. The word length of a
computer is generally defined by the number of bits actually
stored or retrieved in one main memory access.
• Consider a machine with 32 bit address bus. If the word size
is 32 bit, then the high order 30 bit will specify the address of
a word. If we want to access any byte of the word, then it can
be specified by the lower two bit of the address bus.
• For memory operation, the CPU initiates a memory operation by loading the
appropriate data i.e., address to MAR.
• If it is a memory read operation, then it sets the read memory control line to 1.
Then, the contents of the memory location are brought to MDR. The memory
control circuitry indicates this to the CPU by setting MFC to 1.
• If the operation is a memory write operation, then the CPU places the data into
MDR and sets the write memory control line to 1. Once the contents of MDR
are stored in a specified memory location, then the memory control circuitry
indicates the end of the operation by setting MFC to 1.
• A useful measure of the speed of the memory unit is the time that elapses between
the initiation of an operation and the completion of the operation (for example, the
time between Reading and MFC). This is referred to as Memory Access Time.
Another measure is memory cycle time. This is the minimum time delay between
the initiation of two independent memory operations (for example, two
successive memory read operations). Memory cycle time is slightly larger than
memory access time.
 BINARY STORAGE CELL

• The binary storage cell is the basic building block of a memory unit.
• The binary storage cell that stores one bit of information can be modelled by an
SR latch with associated gates.
1 bit Binary Cell (BC)
• The binary cell sotres one bit of information in its internal latch.
• Control input to binary cell

• The storage part is modelled here with SR-latch, but in reality it is an electronics circuit made up of transistors.
• The memory constructed with the help of transistors is known as semiconductor memory.
• The semiconductor memories are termed as Random Access Memory(RAM), because it is possible to access
any memory location in random.
• Depending on the technology used to construct a RAM, there are two types of RAM -
• SRAM: Static Random Access Memory.
• DRAM: Dynamic Random Access Memory.
 M E M O RY T E C H N O L O G I E S

The various memory technologies are:

• 1. SRAM semiconductor memory
• 2. DRAM semiconductor memory
• 3. Flash semiconductor memory
• 4. Magnetic disk
 DYNAMIC RAM (DRAM):

• A DRAM is made with cells that store data as charge on capacitors. The presence or absence of charge
in a capacitor is interpreted as binary 1 or 0.
• Because capacitors have a natural tendency to discharge due to leakage current, dynamic RAM require
periodic charge refreshing to maintain data storage. The term dynamic refers to this tendency of the
stored charge to leak away, even with power continuously applied.
• A typical DRAM structure for an individual cell that stores one bit information is shown in the figure.
 CONTD…

• For the write operation, a voltage signal is applied to the bit line B, a high
voltage represents 1 and a low voltage represents 0.
• A signal is then applied to the address line, which will turn on the transistor T,
allowing a charge to be transferred to the capacitor.
• For the read operation, when a signal is applied to the address line, the
transistor T turns on and the charge stored on the capacitor is fed out onto the
bit line B.
 STATIC RAM (SRAM)

• In an SRAM, binary values are stored using traditional flip-flop constructed with the help of transistors.
• A static RAM will hold its data as long as power is supplied to it.
• A typical SRAM constructed with transistors is shown in the figure.
• Four transistors (T1, T2, T3, T4) are cross connected in an arrangement that
produces a stable logic state.
• In logic state 1, point A1 is high and point A2 is low; in this state T1 and T4 are off,
and T2 and T3 are on .
• In logic state 0, point A1 is low and point A2 is high; in this state T1 and T4 are on,
and T2 and T3 are off .
• Both states are stable as long as the dc supply voltage is applied.
• The address line is used to open or close a switch which is nothing but another
transistor. The address line controls two transistors(T5 and T6).
• When a signal is applied to this line, the two transistors are switched on, allowing
a read or write operation.
• For a write operation, the desired bit value is applied to line B, and its complement is
applied to line . This forces the four transistors(T1, T2, T3, T4) into the proper state.
• For a read operation, the bit value is read from the line B. When a signal is applied to
the address line, the signal of point A1 is available in the bit line B.
 SRAM VERSUS DRAM

• Both static and dynamic RAMs are volatile, that is, it will retain the information as
long as power supply is
• applied.
• A dynamic memory cell is simpler and smaller than a static memory cell. Thus a
DRAM is more dense,
• i.e., packing density is high(more cell per unit area). DRAM is less expensive than
corresponding SRAM.
• DRAM requires the supporting refresh circuitry. For larger memories, the fixed cost of
the refresh circuitry is more than compensated for by the less cost of DRAM cells
• SRAM cells are generally faster than DRAM cells. Therefore, to construct faster
memory modules(like cache memory) SRAM is used.
 D I F F E R E N T I AT E S R A M F R O M D R A M

• SRAMs are simply integrated circuits that are memory arrays with a single access
port that can provide either a read or a write. SRAMs have a fixed access time to
any data.

• SRAMs don’t need to refresh and so the access time is very close to the cycle
time. SRAMs typically use six to eight transistors per bit to prevent the information
from being disturbed when read. SRAM needs only minimal power to retain the
charge in standby mode.

• In a dynamic RAM (DRAM), the value kept in a cell is stored as a charge in a

capacitor. A single transistor is then used to access this stored charge, either to read
the value or to overwrite the charge stored there. Because DRAMs use only a single
transistor per bit of storage, they are much denser and cheaper per bit than SRAM.
 I N T E R N A L O R G A N I Z AT I O N O F M E M O RY C H I P S

A memory cell is capable of storing 1-bit of

information.
A number of memory cells are organized in
the form of a matrix to form the memory
chip.
16X8 memory organization is shown in the
Figure.
• Each row of cells constitutes a memory word, and all cell of a row are connected to a common line which is
referred as word line.
• An address decoder is used to drive the word line. At a particular instant, one word line is enabled
depending on the address present in the address bus. The cells in each column are connected by two lines.
These are known as bit lines.
• These bit lines are connected to data input line and data output line through a Sense/ Write circuit.
• During a Read operation, the Sense/Write circuit sense, or read the information stored in the cells selected
by a word line and transmit this information to the output data line.
• During a write operation, the sense/write circuit receive information and store it in the cells of the selected
word.
• A memory chip consisting of 16 words of 8 bits each, usually referred to as 16 x 8 organization. The data
input and data output line of each Sense/Write circuit are connected to a single bidirectional data line in
order to reduce the pin required.
• For 16 words, we need an address bus of size 4. In addition to address and data lines, two control lines,
and CS, are provided.
• The line is to used to specify the required operation about read or write. The CS (Chip Select) line is
required to select a given chip in a multi chip memory system.
128 x 8 memory chips:
If it is organised as a 128 x 8 memory chips, then it has got 128 memory words
of size 8 bits.
So the size of data bus is 8 bits and the size of address bus is 7 bits (27=128).
 1 0 2 4 X 1 M E M O RY C H I P S :

• If it is organized as a 1024 x 1 memory chips, then it has got

1024 memory words of size 1 bit only.
• Therefore, the size of data bus is 1 bit and the size of address
bus is 10 bits ( ).
• A particular memory location is identified by the contents of
memory address bus.
A decoder is used to decode the memory address.
• There are two ways of decoding of a memory address
depending upon the organization of the memory module.
• In one case, each memory word is organized in a row. In this
case whole memory address bus is used together to decode the
address of the specified location.
 MEMORY HIERARCHY
• Ideally we need fast, large and cheap memory. But unfortunately it’s not possible to get all the three
simultaneously.
• So a various types of memory like above having different characteristics are used. for different purposes
combinedly, which creates a hierarchy of memory module wile being used in computer. This is depicted in
the fig. 17.
 T H E T E M P O R A L A N D S PAT I A L L O C A L I T I E S O F
REFERENCES

•Temporal locality (locality in time): if an item is referenced, it will

tend to be referenced again soon.
•Spatial locality (locality in space): if an item is referenced, items
whose addresses are close by will tend to be referenced soon.
 CACHE MEMORY - WRITING
STRATEGIES

• Write-through is a scheme in which writes always update both the cache and the
next lower level of the memory hierarchy, ensuring that data is always consistent
between the two.
• Write-back is a scheme that handles writes by updating values only to the block in
the cache, then writing the modified block to the lower level of the hierarchy when the
block is replaced.
 MAIN MEMORY - 5 STATE PROCESS
MODEL
• Efficient memory management is vital in a multiprogramming system. If only a few process are in memory, then for much of the time all of
the process will be waiting for I/O and the processor will idle. Thus memory needs to be allocated efficiently to pack as many processes
into main memory as possible.
• When memory holds multiple processes, then the process can move from one process to another process when one process is waiting.
But the processor is so much faster then I/O that it will be common for all the processes in memory to be waiting for I/O. Thus, even with
multiprogramming, a processor could be idle most of the time.
• Due to the speed mismatch of the processor and I/O device, the status at any point in time is reffered to as a state.
• There are five defined state of a process as shown in the figure.
• When we start to execute a process, it is placed in the process queue and it is in the new state. As resources become available, then the
process is placed in the ready queue.
 MAIN MEMORY - 5 STATE PROCESS
MODEL

• 1.New : A program is admitted by the scheduler, but not yet ready to execute. The operating system will
initialize the process by moving it to the ready state.
• 2.Ready : The process is ready to execute and is waiting access to the processor.
• 3.Running : The process is being executed by the processor. At any given time, only one process is in
running
state.
• 4. Waiting : The process is suspended from execution, waiting for some system resource, such as I/O.
• 5. Exit : The process has terminated and will be destroyed by the operating system.
• The processor alternates between executing operating system instructions and executing user processes.
While the operating system is in control, it decides which process in the queue sholud be executed next.
• A process being executed may be suspended for a variety of reasons. If it is suspended because the
process requests I/O, then it is places in the appropriate I/O queue. If it is suspended because of a timeout
or because the operating system must attend to processing some of it's task, then it is placed in ready state.
• We know that the information of all the process that are in execution must be placed in main memory. Since
there is fix amount of memory, so memory management is an important issue.
 SWAPPING

• To utilize the idle time of CPU, we are shifting the paradigm from uniprogram environment to multiprogram environment.
• Since the size of main memory is fixed, it is possible to accomodate only few process in the main memory. If all are waiting
for I/O operation, then again CPU remains idle.
• To utilize the idle time of CPU, some of the process must be off loaded from the memory and new process must be brought
to this memory place. This is known swapping.
What is swapping :
• 1. The process waiting for some I/O to complete, must stored back in disk.
• 2. New ready process is swapped in to main memory as space becomes available.
• 3. As process completes, it is moved out of main memory.
• 4. If none of the processes in memory are ready,
• n Swapped out a block process to intermediate queue of blocked process.
• n Swapped in a ready process from the ready queue.
• But swapping is an I/O process, so it also takes time. Instead of remain in idle state of CPU, sometimes it is advantageous
to swapped in a ready process and start executing it.
• The main question arises where to put a new process in the main memory. It must be done in such a way that the memory
is utilized properly.
 PA R T I T I O N I N G

• Splitting of memory into sections to allocate processes including operating system. There are two scheme
for partitioning :
• Fixed size partitions
• Variable size partitions
Fixed sized pertitions:
• The mamory is partitioned to fixed size partition. Although the partitions are of fixed
• size, they need not be of equal size.
• There is a problem of wastage of memory in fixed size even with unequal size. When a process is brought
into memory, it is placed in the smallest available partition that will hold it.
 PARTITIONING

• Even with the use of unequal size of partitions, there will be wastage of memory. In most cases, a process will not require
exactly as much memory as provided by the partition.
• For example, a process that require 5-MB of memory would be placed in the 6-MB partition which is the smallest
available partition. In this partition, only 5-MB is used, the remaining 1-MB can not be used by any other process, so it is
a wastage. Like this, in every partition we may have some unused memory. The unused portion of memory in each
partition is termed as hole.
Variable size Partition:
• When a processe is brought into memory, it is allocated exactly as much memory as it requires and no more. In this
process it leads to a hole at the end of the memory, which is too small to use.
• It seems that there will be only one hole at the end, so the waste is less. But, this is not the only hole that will be present
in variable size partition.
• When all processes are blocked then swap out a process and bring in another process.
• The new swapped in process may be smaller than the swapped out process.
• Most likely we will not get two process of same size. So, it will create another whole.
• If the swap- out and swap-in is occuring more time, then more and more hole will be created, which will lead to more
wastage of memory.
 PARTITIONING

There are two simple ways to slightly remove the problem of memory wastage:
• Coalesce : Join the adjacent holes into one large hole , so that some process can be accomodated into
the hole.
• Compaction : From time to time go through memory and move all hole into one free block of memory.
• During the execution of process, a process may be swapped in or swapped out many times. it is obvious
that a process is not likely to be loaded into the same place in main memory each time it is swapped in.
Further more if compaction is used, a process may be shiefted while in main memory.
• A process in memory consists of instruction plus data. The instruction will contain address for memory
locations of two types:
• Address of data item
• Address of instructions used for branching instructions
 PA R T I T I O N I N G

• These addresses will change each time a process is swapped in. To solve this problem, a distinction is made between
logical address and physical address.
• Logical address is expressed as a location relative to the begining of the program. Instructions in the program contains only
logical address.
• Physical address is an actual location in main memory.
• When the processor executes a process, it automatically converts from logical to physical address by adding the current
starting location of the process, called it's base address to each logical address.
• Every time the process is swapped in to main memory, the base address may be diffrent depending on the allocation of
memory to the process.
• Consider a main memory of 2-MB out of which 512-KB is used by the Operating System. Consider three process of size
425-KB, 368-KB and 470-KB and these three process are loaded into the memory. This leaves a hole at the end of the
memory. That is too small for a fourth process. At some point none of the process in main memory is ready.
• The operating system swaps out process-2 which leaves sufficient room for new process of size 320-KB. Since process-4 is
smaller then process-2, another hole is created. Later a point is reached at which none of the processes in the main memory
is ready, but proces-2, so process-1 is swapped out and process-2 is swapped in there. It will create another hole. In this
way it will create lot of small holes in the momory system which will lead to more memory wastage.
THE EFFECT OF DYNAMIC
PARTITIONING