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UNIVERSITY INSTITUTE OF

ENGG.
DEPARTMENT OF ECE
Bachelor of Engineering (Electronics And
Communication Engineering)
Microprocessor and Microcontroller
21ECH–224

DISCOVER . LEARN .
8086 Architecture
EMPOWER
Microprocessor
and
Microcontroller
CO
1
Understand and gain detailed knowledge about software and
hardware structure of the Microprocessor and Microcontroller.
CO
Course
2 Outcome
Apply the acquired knowledge and analyze programming proficiency
for 8086 microprocessor.
CO
3
Apply the acquired knowledge and analyze the programming skills
for 8051 microcontroller.
CO
4
Illustrate how the communication and different peripherals are
interfaced with Microcontroller.
CO
5
Design assembly language programs for microprocessor and
microcontroller to provide solution to control problems.

2
Historical Background

• Invention of first Microprocessor

• Invention of first Microcontroller

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MOORE’S LAW

“Cramming more
Components on
Integrated Circuits “

What it actually says is that


the number of transistors
that can be packed into a
given unit of space
will roughly double every
two years though the cost
of computers is halved

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Evolution of micrprocessors

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Evolution Contd.

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EVOLUTION Summary
Generation Microproc Year Size of Clock speed No. of No. of
essor up transistor instruction
s execute per
second

First Intel 4004 1971 4 bit 740KHz 2300 60,000


Generation
Intel 4040 1974 4 bit 500-740KHz 3000 50,000-60,000
Intel 8008 1972 8 bit 500 KHz 3500 50,000
Intel 8080 1974 8 bit 2 MHz 6000 5,00,000
Second Intel 8085 1976 8 bit 3 MHz 6500 7,69,230
Generation
Third Intel 8086 1978 16 bit 5-10MHz 29,000 2.5 million
Generation
Intel 8088 1979 16 bit 5-10MHz 29,000 2.5 million
Intel80286 1982 16 bit 8 MHz 1,34,000 4 million

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Contd.
Generation Microproces Year Size of up Clock speed No. of
sor transistors

Fourth Intel80386 1985 32 bit 16-33 MHz 2,75,000


Generation Intel80486 1989 32 bit 25 -100MHz 1.2million
Pentium 1993 32/64 bit 60 MHz 3.1million
Fifth Pentium II 1997 64 bit 233 MHz 7.5million
Generation Pentium III 1999 64 bit 450 MHz 9.5million
Pentium IV 2000 64 bit 1.5 GHz 42million
Intel Atom 2008 32/64 0.6-2.13GHz 47million
Intel Dual 2006 32/64 1.3-2.6 228 million
Core
Intel core 2 2006 64 1.06-3.33 291 million

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Contd.
Geneartion Microprocessor Year Clock speed

Fifth Intel core i3 2008 1.2-3.7 GHz


Generation

Intel core i5 2009 1.06-3.6 GHz

Intel core i7 2010 1.6-4.4 GHz

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Exercise

1. Which generation your personal computer/laptop


belongs to?
2. What are the latest set of processors used?

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Basic Microcomputer System

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Basic Terms used in
Microprocessor
Instruction Set The group of commands that the microprocessor can understand is
called Instruction set. It is an interface between hardware and
software.
Bus Set of conductors intended to transmit data, address or control
information to different elements in a microprocessor. A
microprocessor will have three types of buses, i.e., data bus, address
bus, and control bus.
Instruction per It is a measure of how many instructions a CPU is capable of executing
Cycle in a single clock.
Machine Cycle It is a measure of time taken by CPU to executing a single instruction

Clock Speed It is the number of operations per second the processor can perform. It
can be expressed in megahertz (MHz) or gigahertz (GHz). It is also called
the Clock Rate.
Word Length The number of bits the processor can process at a time is called the
word length of the processor. 8-bit Microprocessor may process 8 -bit
data at a time. TheUIE,
range of word length is from 4 bits to 64 bits
ECE Deptt.
depending upon the type of the microcomputer.
Contd.
Data Types The microprocessor supports multiple data type formats like binary,
ASCII, signed and unsigned numbers.
Tri state Buffer Tri-state or 3-state logic allows an output port to assume a high
impedance state, effectively removing the output from the circuit, in
addition to the 0 and 1 logic levels. This allows multiple circuits to
share the same output line or lines

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How Microprocessor Works

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Features of Microprocessor

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Exercise

1. Which generation your personal computer/laptop


belongs to?
2. What are the latest set of processors used?

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Architecture of 8086
The architecture of 8086 includes
Arithmetic Logic Unit (ALU)
Flags
General registers
Instruction byte queue
Segment registers
EU & BIU
The 8086 CPU logic has been partitioned into two functional
units namely Bus Interface Unit (BIU) and Execution Unit (EU).

The major reason for this separation is to increase the


processing speed of the processor.

The BIU has to interact with memory and input and output
devices in fetching the instructions and data required by the
EU.

EU is responsible for executing the instructions of the


programs and to carry out the required processing .
EU & BIU
BUS INTERFACE UNIT (BU)

The BIU performs all bus operations for EU .


• Fetching instructions
• Responsible for executing all external bus cycles.
• Read operands and write result.

EXECUTION UNIT (EU)


• Execution unit contains the complete infrastructure
required to execute an instruction.
Architecture Diagram
Execution Unit
The Execution Unit (EU) has
Control unit
Instruction decoder
Arithmetic and Logical Unit (ALU)
General registers
Flag register
Pointers
Index registers
Execution Unit
• Control unit is responsible for the co-ordination of
all other units of the processor
• ALU performs various arithmetic and logical
operations over the data
• The instruction decoder translates the instructions
fetched from the memory into a series of actions
that are carried out by the EU
Execution Unit - Registers
• General registers are used for temporary storage
and manipulation of data and instructions
• Accumulator register consists of two 8-bit registers
AL and AH, which can be combined together and
used as a 16-bit register AX
• Accumulator can be used for I/O operations and
string manipulation
Execution Unit - Registers
• Base register consists of two 8-bit registers BL and BH,
which can be combined together and used as a 16-bit
register BX
• BX register usually contains a data pointer used for
based, based indexed or register indirect addressing.
Similar to 8085 H-L register.
• Count register consists of two 8-bit registers CL and
CH, which can be combined together and used as a
16-bit register CX
• Count register can be used as a counter in string
manipulation and shift/rotate instructions
Execution Unit - Registers
• Data register consists of two 8-bit registers DL and
DH, which can be combined together and used as a
16-bit register DX
• Data register can be used to hold 16 bit result in 16 in
16x16 multiplication.
Execution Unit - Registers
Pointer Registers
Stack pointer and BP are used to access data in the
stack segment.
SP is used as an offset from the current SS during
execution of instructions that involve the stack
segment in external memory.
BP is used in based addressing mode.
Execution Unit - Registers
Index Register
Source index register (SI) and Destination Index
Registers are used in indexed addressing.
Execution Unit - Registers
Execution Unit - Flags
Execution Unit - Flags
• Overflow Flag (OF) - set if the size of the exceeds the
capacity of the destination location.
• Direction Flag (DF) – It is used with string operations.
When set , it causing string instructions to auto –
decrement or to process strings from right to left.
• Interrupt-enable Flag (IF) - setting this bit enables
maskable interrupts . When IF = 0 , all maskable
interrupt are disable.
• Single-step Flag (Trap F) – put 8086 in the single step
mode.
Execution Unit - Flags
• Sign Flag (SF) - set if the most significant bit of the
result is one.
• Zero Flag (ZF) - set if the result is zero.
• Auxiliary carry Flag (AF) - set if there was a carry from
or borrow to bits 0-3 in the AL register.
• Parity Flag (PF) - set if parity (the number of "1" bits)
in the low-order byte of the result is even.
• Carry Flag (CF) - set if there was a carry from or
borrow to the most significant bit during last result
calculation
Execution Unit - Flags
Exercise 1

Q. Give the status of different flags when the microprocessor


performs the following arithmetic operations in ALU (+127)d +
(-2)d. d stands for decimal number.

UIE, ECE Deptt.


Execution Unit - Pointers
Stack Pointer (SP) is a 16-bit register pointing to program
stack
Base Pointer (BP) is a 16-bit register pointing to data in
stack segment. BP register is usually used for based,
based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for
indexed, based indexed and register indirect addressing,
as well as a source data addresses in string manipulation
instructions.
Destination Index (DI) is a 16-bit register. DI is used for
indexed, based indexed and register indirect addressing,
as well as a destination data addresses in string
manipulation instructions.
Execution Unit - Pointers
Bus Interface Unit
• The BIU has
• Instruction stream byte queue
• A set of segment registers
• Instruction pointer
BIU – Instruction Byte Queue
• 8086 instructions vary from 1 to 6 bytes
• Therefore fetch and execution are taking place
concurrently in order to improve the performance of
the microprocessor
• The BIU feeds the instruction stream to the execution
unit through a 6 byte prefetch queue
BIU – Instruction Byte Queue
• Execution and decoding of certain instructions do
not require the use of buses
• While such instructions are executed, the BIU
fetches up to six instruction bytes for the following
instructions (the subsequent instructions)
• The BIU store these prefetched bytes in a first-in-
first out register by name instruction byte queue
• When the EU is ready for its next instruction, it
simply reads the instruction byte(s) for the
instruction from the queue in BIU
Segment: Offset Notation
• The total addressable memory size is 1MB
• Most of the processor instructions use 16-bit
pointers the processor can effectively address only
64 KB of memory
• To access memory outside of 64 KB the CPU uses
special segment registers to specify where the
code, stack and data 64 KB segments are positioned
within 1 MB of memory
Segment: Offset Notation
• A simple scheme would be to order the bytes in a
serial fashion and number them from 0 (or 1) to the
end of memory
• The scheme used in the 8086 is called segmentation
• Every address has two parts, a SEGMENT and an
OFFSET (Segmnet:Offset )
• The segment indicates the starting of a 64 kilobyte
portion of memory, in multiples of 16
• The offset indicates the position within the 64k
portion
• Absolute address = (segment * 16) + offset
Segment Registers
• The memory of 8086 is divided into 4 segments
namely
• Code segment (program memory)
• Data segment (data memory)
• Stack memory (stack segment)
• Extra memory (extra segment)
Different Areas in Memory
• Program memory – Program can be located
anywhere in memory
• Data memory – The processor can access data in
any one out of 4 available segments
• Stack memory – A stack is a section of the memory
set aside to store addresses and data while a
subprogram executes
• Extra segment – This segment is also similar to data
memory where additional data may be stored and
maintained
Segment Registers
• Code Segment (CS) register is a 16-bit register
containing address of 64 KB segment with processor
instructions
• The processor uses CS segment for all accesses to
instructions referenced by instruction pointer (IP)
register
• Stack Segment (SS) register is a 16-bit register
containing address of 64KB segment with program
stack
• By default, the processor assumes that all data
referenced by the stack pointer (SP) and base pointer
(BP) registers is located in the stack segment
Segment Registers
• Data Segment (DS) register is a 16-bit register
containing address of 64KB segment with program
data
• By default, the processor assumes that all data
referenced by general registers (AX, BX, CX, DX) and
index register (SI, DI) is located in the data segment
• Extra Segment (ES) register is a 16-bit register
containing address of 64KB segment, usually with
program data
• By default, the processor assumes that the DI register
references the ES segment in string manipulation
instructions
Segment Registers

If a location 109F0 of Code Segment is to be addressed to fetch


An instruction, the physical address will be calculated as follows
CSR = 010A
IP = F950
Effective Address = 109F0
References

1.B. Ram, “Fundamentals of Microprocessor and Microcomputers”, 6th


edition 2005, Dhanpat Rai Publications
2. Hall, DV; Rap, SSSP; Ye, K. Microprocessors and Interfacing, Mc Graw Hill
India
3. http://www.intel.com/pressroom/kits/quickreffam.htm#i486
4.https://nptel.ac.in/content/storage2/courses/106108100/pdf/
Teacher_Slides/mod1/M1L3.pdf
5. http://www.vssut.ac.in/lecture_notes/lecture1428551326.pdf

UIE, ECE Deptt.


THANK YOU

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