22 System Debugging

System Debugging using Logic Debug
Cores and SDK
Zynq
Vivado 2015.2 Version
This material exempt per Department of Commerce license exception TSU © Copyright 2015 Xilinx
Objectives
After completing this module, you will be able to:

– List various available debug cores in Vivado and their functionality
– Describe the process of including the Vivado Design Suite debug tool sampling cores
– State how the Vivado integrated logic analyzer, SDK Debug perspective, and XMD/TCF tools facilitate
hardware and software debugging
System Debugging 22-2 © Copyright 2015 Xilinx

Outline
Introduction
Hardware Debugging
Software Debugging
System Debugging
Summary

Introduction
Debugging is an integral part of the embedded systems development

The debugging process is defined as testing, stabilizing, localizing, and correcting
errors
Two methods of debugging:
– Hardware debugging via a logic probe, logic analyzer, in-circuit emulator, or background debugger
– Software debugging via a debugging instrument
• A software debugging instrument is dedicated hardware and part of the silicon that is accessible via JTAG or
dedicated part pins
• Controls the processor as an intrusive debug unit that is disabled during normal operation
• Some "hard" processors have this feature permanently available while "soft" processors may have this physically
removed from the delivered product
Debugging types:
– Functional debugging
– Performance debugging

Xilinx Solution for Debugging Embedded Designs
Hardware debugging tool

– Vivado logic analyzer for hardware; functionally replaces expensive external logic analyzer
Software debugging tools
– SDK Debugging perspective and inexpensive JTAG cable replace ICE
Built-in, cross-probing trigger capability for hardware and software debug coherency
– Vivado logic analyzer invoked through Vivado
– SDK Debugging perspective tool accessed from within SDK
A single JTAG connection can be used for
– Programming the programmable logic
– Downloading application
– Hardware and software debugging

Outline
Introduction
Hardware Debugging
Software Debugging
System Debugging
Summary

Vivado Logic Analyzer System
Vivado logic analyzer tool cores provide full internal

visibility to all soft IP
– Access to hard IP ports
– Accesses all the internal signals and nodes within the
programmable logic (ILA)
– Stimulus can be applied using the Virtual I/O core (VIO)
Debugging occurs at, or near, system speeds
– Debug on-chip using the system clock
Minimize pins needed for debugging
– Access via the JTAG interface

Vivado Debug Tool Access Points
Select Tools > Set up Debug to launch the Vivado Debug Wizard
Once the wizard has been run, a Debug tab appears
– Right-click the debug_core_hub icon in this window to relaunch the wizard
• Add signals
• Add new ILAs
• View resources
• Create debug core or port
• Implement the cores

AXI Performance Monitor Core
Enables AXI system performance

measurement for multiple slots
– AXI4 and AXI4-Stream
AXI Performance Monitor supports
analyzing system behavior on AXI
interfaces
– Event logging
• Captures AXI events and external events
• Time stamp between two successive events into
streaming FIFO
– Event counting
• Measure events on AXI4/AXI4-Stream monitor
slots or external event ports

VIO Core
Support for monitoring and driving internal programmable logic signals in real time
Probe input unit
Probe output unit

ILA Core
Used for monitoring internal programmable logic signals for post-analysis

Multiple configurable ILA trigger units
– Configurable trigger input widths and match types for use with different input signals types
Up to 64 probes through GUI
– Up to 1024 probes through tcl command
Sequential triggering
Storage qualification
Configurable cross triggering
– Trigger in and Trigger out interfaces
Pre- and post-trigger buffering (capture data
before, during, and after trigger condition is met)

Core Resources Usage
Debug tools like to use as much block RAM as available

More block RAM equates to larger (deeper and/or wider) trace buffers
Use larger devices for debugging prototypes to provide extra block RAM
If the application is utilizing too much block RAM, temporarily modify hardware
applications to free up block RAM for debugging usage—small FIFOs and buffer
memory, for example

Selecting Signals to Debug
Select nets in the Vivado tool by any means

– Netlist view (nets folders)
• Each level of logic hierarchy
– Schematic
– Find results
Right-click the net and select Mark Debug
Nets added to Unassigned Nets folder in the Debug
tab view
– Placeholder for probable nets prior to configuring cores
Net name search also in the Set Up Debug Wizard
Add nets using xdc command
– set_property mark_debug true [get_nets sine*]

Debug Tool Configuration
The Vivado tool view displays core content

and configuration
– CLK, PROBE
– Signal count
Set options for cores and signals in the
Properties view

Exploring Core Logic
Netlist window populated with

implemented core logic
– debug_core_hub displayed in Netlist view
– Expandable logic
Analyze internal core logic
– Resource statistics
– Schematic
– Connectivity
Floorplan the cores

Vivado Debug Core Integration
Support for new ILA v5.x core

Requires at least synthesized netlist
Interactively select signals to probe
– From Netlist and Schematic views, Find command
Wizard walks through the process
– Configure clocks, triggers, multiple cores
– Reports number of cores, type, and clock
Updates to your design netlists
– Inserts and compiles the cores
– All subsequent runs will use cores
Maintain inserted cores
– Modify probed signals, configuration
Launch the analyzer after running BitGen

Outline
Introduction
Hardware Debugging
Software Debugging
System Debugging
Summary

Software Debugging Support in XSDK
XSDK supports software debugging via:

– GNU Debugger (GDB)
• Software debugger that runs on PC
– Xilinx Microprocessor Debugger (XMD)
• Facilitates an interface between the GNU tools and the hardware
– Zynq All Programmable SoC contains own internal trace port
• Performs same general tasks as MDM does in a MicroBlaze system
– GDB debug IDE communicates with hardware through XMD in software
– New TCF(Target Communication Framework) debugger over digilent cable for ARM
• Open source
• Supports system level debugging
• Improved performance

Configure the Programmable Logic
Before debugging session can be launched, the target programmable logic must be
configured
– PL would have logic analyzer core(s) for hardware debugging
Design must contain a hardware debug connection
– CoreSight – built into the Zynq ARM Cortex-A9 processor
– MDM – add in the MicroBlaze based system
Verify in the Console view that download succeeded
– Done pin goes High

Create Debug Configuration

SDK Debug Perspective
Stack frame for target threads

Variables, breakpoints, and registers views
C/C++ editor
Code outline
– Disassembly view can be added using
Window > Show View > Disassembly
Console, SDK Log, and Memory views

Outline
Introduction
Hardware Debugging
Software Debugging
System Debugging
Summary

What is System Debugging?
System debugging is determining where the bug is:

– In hardware?
– In software?
How is system debugging possible?
– Set breakpoint in GDB: when hit → triggers the Vivado logic analyzer
– Set trigger in Vivado logic analyzer: when hit → halts CPU and debugger stops

System Debug: Simultaneous Hardware and Software
Debugging (1)
XMD supports simultaneous access Vivado logic analyzer running on the

over Xilinx download cables host
ILA core in the target cores Debugger on the host
Software condition triggers hardware:
– Software breakpoint asserts the P2F_trig
signal and if the ILA is sensitive to this
signal, it will capture
Hardware condition triggers software:
– Match in the ILA asserts the F2P_Trig
signal, which halts the processor

System Debug: Simultaneous Hardware and Software
Debugging (2)
Cross triggering connections between Zynq

processor and ILA
XMD and TCF support simultaneous access over
Xilinx download cables
– ILA instantiations
– Treated like the peripheral cores
Set breakpoint in the SDK Debugging
perspective: when hit, triggers the logic analyzer
Set trigger in logic analyzer: when hit, halts CPU
and debugger stops

Simultaneous Hardware and Software Debugging

Outline
Introduction
Hardware Debugging
Software Debugging
System Debugging
Summary

Summary
Debugging is an integral part of the embedded systems development

Vivado and SDK provides tools to facilitate hardware and software debugging
– Hardware debugging is done through using Vivado logic analyzer cores
– Software debugging is performed using xmd and GNU debugger or system debugger
SDK provides environment, perspective, and underlying tools to enable seamless
software debugging
A significant amount of hardware overhead may occur depending on the type and
number of cores and sample depth
The Debug Configuration wizard simplifies hardware connections and the cores
inclusion
With software debugging and the Vivado logic analyzer supporting cross-probing
enables simultaneous hardware and software debugging
– Use it to find and fix embedded system bugs faster

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System Debugging using Logic Debug

Cores and SDK

After completing this module, you will be able to:

System Debugging 22-2 © Copyright 2015 Xilinx

System Debugging 22-3 © Copyright 2015 Xilinx

Debugging is an integral part of the embedded systems development

System Debugging 22-4 © Copyright 2015 Xilinx

Hardware debugging tool

System Debugging 22-5 © Copyright 2015 Xilinx

System Debugging 22-6 © Copyright 2015 Xilinx

Vivado logic analyzer tool cores provide full internal

System Debugging 22-7 © Copyright 2015 Xilinx

System Debugging 22-8 © Copyright 2015 Xilinx

Enables AXI system performance

System Debugging 22-9 © Copyright 2015 Xilinx

System Debugging 22-10 © Copyright 2015 Xilinx

Used for monitoring internal programmable logic signals for post-analysis

System Debugging 22-11 © Copyright 2015 Xilinx

Debug tools like to use as much block RAM as available

System Debugging 22-12 © Copyright 2015 Xilinx

Select nets in the Vivado tool by any means

System Debugging 22-13 © Copyright 2015 Xilinx

The Vivado tool view displays core content

System Debugging 22-14 © Copyright 2015 Xilinx

Netlist window populated with

System Debugging 22-15 © Copyright 2015 Xilinx

Support for new ILA v5.x core

System Debugging 22-16 © Copyright 2015 Xilinx

System Debugging 22-17 © Copyright 2015 Xilinx

XSDK supports software debugging via:

System Debugging 22-18 © Copyright 2015 Xilinx

System Debugging 22-19 © Copyright 2015 Xilinx

System Debugging 22-20 © Copyright 2015 Xilinx

Stack frame for target threads

System Debugging 22-21 © Copyright 2015 Xilinx

System Debugging 22-22 © Copyright 2015 Xilinx

System debugging is determining where the bug is:

System Debugging 22-23 © Copyright 2015 Xilinx

XMD supports simultaneous access Vivado logic analyzer running on the

System Debugging 22-24 © Copyright 2015 Xilinx

Cross triggering connections between Zynq

System Debugging 22-25 © Copyright 2015 Xilinx

System Debugging 22-26 © Copyright 2015 Xilinx

System Debugging 22-27 © Copyright 2015 Xilinx

Debugging is an integral part of the embedded systems development

System Debugging 22-28 © Copyright 2015 Xilinx

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