Apex Institute of Technology

Department of Computer Science & Engineering

Computer Organization & Architecture

(CST-281)

Jayashree Mohanty
E15737
Assistant Professor DISCOVER . LEARN . EMPOWER
1
CSE(AIT), CU
About Course
This course is introduced to 4th semester students of
BE
This course offers a good understanding of the various
functional units of a computer system and prepares the
students to be in a position to design a basic computer
system
In addition to this students will be exposed to the recent
trends in parallel and distributed computing and
multithreaded application
Basic Organization
Memory Cell Operation
• Represent two stable/semi-stable states representing
1 and 0
• Capable of being written to at least once
• Capable of being read multiple times
Semiconductor Memory Types
• Random Access Memory (RAM)
• Read Only Memory (ROM)
• Programmable Read Only Memory (PROM)
• Eraseable Programmable Read Only Memory (EPROM)
• Electronically Eraseable Programmable Read Only Memory (EEPROM)
• Flash Memory
 Random Access Memory

• Random Access Memory refers to accessing individual memory

locations directly by address
• RAM allows reading and writing (electrically) of data at the byte level
• Two types
• Static RAM
• Dynamic RAM
• Volatile
 Read Only Memory (ROM)
• Sometimes can be erased for reprogramming, but might
have odd requirements such as UV light or erasure only at
the block level
• Sometimes require special device to program, i.e.,
processor can only read, not write
• Types
• EPROM
• EEPROM
• Custom Masked ROM
• OTPROM
• FLASH
ROM Uses
• Permanent storage – nonvolatile
• Microprogramming
• Library subroutines
• Systems programs (BIOS)
• Function tables
• Embedded system code
EPROM
• Written to only with a programmer.
• Erased with ultraviolet light
• Positive
• non-volatile storage without battery
• can write to it, but only with aid of programmer
• Negative
• programmer requirements
• Expensive
• locations must be erased before writing
 EEPROM
• Written to with either programmer or the processor
(electrically)
• Erased with either a programmer or the processor (byte-
by-byte electrically)
• Positive
• non-volatile memory without batteries
• programmable a single-location at a time
• Negative
• Expensive
• only smaller sizes available
• extremely slow write times (10 mS vs. 100 to 200 nS)
 Custom masked ROM
• You send the ROM manufacturer your data and they mask
it directly to the ROM
• Use only when you are selling large volume of a single
product
• Positive
• becomes cheaper to use for approximately more than 2000 parts
• components come from chip manufacturer already programmed
and tested taking out a manufacturing step
• Negative
• costs several thousand dollars for custom mask
• software changes are costly
• cannot be reprogrammed
 OTPROM
• Uses fuses that are burned to disconnect a logic 1 and turn it to a
logic 0.
• Written to by you using a programmer similar to EPROM
• Once it's written to, the data is in there forever.
• Positive
• cheaper than EPROM due to cheaper packaging
• more packaging options than EPROM due to less constraints like
erasure window
• standard "off-the-shelf" component
• cheaper than Custom masked ROM up to about 10,000 devices
• Negative – to reprogram, have to throw out the chip - Should only
be used for stable design
 FLASH
• These memories are basically EEPROMs except that
erasure occurs at the block level in order to speed up the
write process
• Non-volatile
• This makes FLASH work like a fast, solid state hard drive
• Positive
• non-volatile
• higher densities than both SRAM and DRAM
• Negative
• process of storing data is at a block level (and slower)
• data cell must be erased before writing data to it
Flash Density Comparison

Source: Griffin, J., Matas, B., de Suberbasaux, C., ”Memory 1996” ,

Integrated Circuit Engineering Corporation, Scottsdale, AZ, on-line:
http://smithsonianchips.si.edu/ice/cd/MEM96/TITLE.PDF
Memory Cell Operation
 Dynamic RAM (DRAM)
• Bits stored as charge in capacitors
• Simpler construction
• Smaller per bit
• Less expensive
• Slower than SRAM (maintenance and read overhead explained
later)
• Typical application is main memory
• Essentially analogue -- level of charge determines value
DRAM Structure
 DRAM Operation
• Address line active when bit read or written
• Logic ‘1’ closes transistor switch (i.e., current flows)
• Write
• Voltage to bit line – High for 1 low for 0
• Signal address line – Controls transfer of charge to capacitor
• Read
• Address line selected – transistor turns on
• Charge from capacitor fed via bit line to sense amplifier
• Compares with reference value to determine 0 or 1
 Static RAM (SRAM)
• Essentially uses latches to store charge (transistor circuit)
• As long as power is present, transistors do not lose charge (no
refresh)
• Very fast (no sense circuitry to drive nor charge depletion)
• Can be battery-backed – A small battery is piggy-backed to the RAM
chip an allows data to remain even when power is removed (Not
possible with DRAM)
• More complex construction
• Larger per bit
• More expensive
• Used for Cache RAM because of speed and no need for large volume
or high density
SRAM Operation
(Figure 5.2b from textbook)
 SRAM Operation
• Transistor arrangement gives stable logic state
• State 1
• C1 high, C2 low
• T1 T4 off, T2 T3 on
• State 0
• C2 high, C1 low
• T2 & T3 off, T1 & T4 on
• Address line transistors
• T5 & T6 act as switches connecting cell
• Write – apply value to B & compliment to B
• Read – value is on line B
 SRAM vs. DRAM
• Both volatile – Power needed to preserve data
• DRAM
• Simpler to build, smaller
• More dense
• Less expensive
• Needs refresh
• Larger memory units
• SRAM
• Faster
• Used for cache
DRAM Organization Details
(by example)
• A 16Mbit chip can be organised as a 2048 x 2048 x 4 bit array
• This arrangement reduces the number of address pins
• Multiplex row address and column address
11 pins to address (211=2048)
• Adding one more pin doubles range of values for rows and for
columns and therefore increases capacity by factor of four
DRAM Organization Details (continued)
DRAM Process
• Total number of address lines is half that of the total needed for the
addressable locations
• A single addressable memory location has the address divided in half,
e.g., the MSB half representing the row address and the LSB half
representing the column address. This saves on pins.
DRAM Process (continued)

• ^RAS (row address select) strobes the row address in to its buffer or
latch while ^CAS (column address select) strobes the column address
into its buffer or latch.
• Note: one more pin on the address quadruples the size of the matrix
(doubles rows and doubles columns for an increase by factor of four)
• To make 16 bit wide data bus, you'll need four of these example
modules
DRAM Refresh
• Two things discharge a DRAM capacitor
• Data read
• Leakage current
• Need refreshing even when powered and idle (once every
few milliseconds)
• Refresh circuit included on chip – Even with added cost,
still cheaper than SRAM cost
• Refresh process involves disabling chip, then reading data
and writing it back
• Performed by counting through “rows”
• Takes time – Slows down apparent performance
DRAM Organization Example
Module
Organization:
Using multiple
memories in
parallel to
increase data
bus width
Module Organization: Using chip selects to
increase the number of words
Advanced DRAM Organization

• SRAM Cache was the traditional way to improve performance of the

DRAM
• Basic DRAM is unchanged since first RAM chips
• Enhanced DRAM
• Contains small SRAM as well
• SRAM acts as cache holding last line read
• Cache DRAM (CDRAM)
• Larger SRAM added
• Acts as either cache or serial buffer
FPM and EDO DRAM
• Fast Page Mode (FPM) shortens cycle time by allowing
processor to use the same row address, but a different
column address (removes one step in the addressing
sequence)
• The data of a single row is referred to as a "page"
• Extended Data-Out (EDO) allows the processor to
overlap the data read cycle with the write for the next
column address
• EDO result is a savings of approximately 10 ns for each
read within a single page
Synchronous DRAM (SDRAM)
• Access is synchronized with an external clock
• Address is presented to RAM
• RAM finds data (CPU waits in conventional DRAM)
• Since SDRAM moves data in time with system clock, CPU
knows when data will be ready
• CPU does not have to wait, it can do something else
• Burst mode allows SDRAM to set up stream of data and
fire it out in block
• DDR-SDRAM sends data twice per clock cycle (leading &
trailing edge)
SDRAM Sample Timing
 RAMBUS or RDRAM
• Suggests transfer rates from 1.6 to 10.7 GBytes per second.
• Subsystem consists of the memory array, the RAM
controller, and a well-defined bus
• Bus definition includes all components including the
microprocessor and any other devices that may use it
• Vertical package (all pins on one side) called Rambus in-line
memory modules (RIMMs)
• Adopted by Intel for Pentium & Itanium
 Bus
• In computer architecture, a bus (shortened form of the Latin
omnibus, and historically also called data highway or databus)
is a communication system that transfers data between
components inside a computer, or between computers. This
expression covers all related hardware components (wire,
optical fiber, etc.)
• Communication protocol is packet-based
• Implements pipelined operation overlapping command and
data
• 800 to 1200 MHz operation
• Inititial access time = 480ns
• After that, 1.6 GBps
• Data exchange over 28 wires
MEMORY ORGANIZATION

• Memory Hierarchy

• Main Memory

• Auxiliary Memory

• Associative Memory

• Cache Memory

• Virtual Memory

• Memory Management
Hardware
MEMORY HIERARCHY

Memory Hierarchy is to obtain the highest possible

access speed while minimizing the total cost of the memory
system
Auxiliary memory
Magneti
c tape I/O Main
s processor memory
Magneti
c disks

CPU Cach
memory
e

Registe
r

Cach
e

Main Memory

Magnetic Disk

Magnetic Tape
 Main Memory

MAIN MEMORY
RAM and ROM
Chips
Typical RAM chip
Chip select CS1
1
Chip select CS
2 Rea 2
RD 128 x 8-bit data
d 8RAM bus
Write WR
7-bit AD 7
address

CS1 CS2 RD WR Memory function State of data

0 0 x x Inhibit bus
High-
0 1 x x Inhibit impedence
High-
1 0 0 0 Inhibit High-
impedence
1 0 0 1 Write Input data to
impedence
1 0 1 x Output
RAM data from RAM
1 1 x x Inhibit
Read High-
impedence

Typical ROM chip

Chip select CS1
1
Chip select CS
2 2 512 x 8-bit data
8ROM bus
9-bit address AD 9
 Main Memory

MEMORY ADDRESS MAP

Address space assignment to each memory chip

Example: 512 bytes RAM and 512 bytes ROM

Hexa Address bus

Component address 10 9 8 7 6 5 4 3 2 1
RAM 1 0000 - 007F 0 0 0 x x x x x x x
RAM 2 0080 - 00FF 0 0 1 x x x x x x x
RAM 3 0100 - 017F 0 1 0 x x x x x x x
RAM 4 0180 - 01FF 0 1 1 x x x x x x x
ROM 0200 - 03FF 1 x x x x x x x x x

Memory Connection to CPU

- RAM and ROM chips are connected to a CPU
through the data and address buses

- The low-order lines in the address bus select

the byte within the chips and other lines in the
address bus select a particular chip through
its chip select inputs
 Main Memory

CONNECTION OF MEMORY TO CPU

Address CP
bus 9 8
16-11 10 7-1 U WR
RD Data bus

Decoder
3 2 1 0
CS1
CS2

Data
RD 128 x 8
RAM 1
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 2
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 3
WR
AD7

CS1
CS2

Data
RD 128 x 8
RAM 4
WR
AD7

CS1
CS2

Data
1- 7 512 x 8
8
9 } AD
9
ROM
 Auxiliary Memory

AUXILIARY MEMORY
Auxiliary memory units are among computer peripheral equipment. They trade
slower access rates for greater storage capacity and data stability. Auxiliary
memory holds programs and data for future use, and, because it is nonvolatile
(like ROM), it is used to store inactive programs and to archive data.

Moving Head Disk Fixed Head Disk

Organization of Disk
Hardware

Track
 Associative Memory

ASSOCIATIVE MEMORY
- Accessed by the content of the data rather than by an address
Hardware
- Also called Content Addressable Memory (CAM)
Organization

Argument register(A)

Key register (K)

Match
register

Input Associative
memory
array and
logic M
Rea m words
d
Write n bits per word

- Compare each word in CAM in parallel with the

content of A(Argument Register)
- If CAM Word[i] = A, M(i) = 1
- Read sequentially accessing CAM for CAM Word(i) for M(i) =
1
- K(Key Register) provides a mask for choosing a
particular field or key in the argument in A
(only those bits in the argument that have 1’s in
their corresponding position of K are compared)
 Associative Memory

ORGANIZATION OF CAM
A1 Aj An

K1 Kj Kn

Word 1 C11 C1j C1n M1

Word i Ci1 Cij Cin Mi

Word m Cm Cm Cm Mm
1 j n
Bit 1 Bit j Bit n

Internal organization of a typical cell Cij

Aj Kj
Input

Write

R S
F ij Match To M i
Rea logic
d

Output
 Associative Memory

MATCH LOGIC

K1 A1 K2 A2 Kn An

F'i1 F i1 F'i2 F i2 .... F'in F in

Mi
 Cache Memory

CACHE MEMORY
Locality of Reference
- The references to memory at any given time
interval tend to be confined within a localized areas
- This area contains a set of information and
the membership changes gradually as time goes by
- Temporal Locality
The information which will be used in near future
is likely to be in use already( e.g. Reuse of information in loops)
- Spatial Locality
If a word is accessed, adjacent(near) words are likely accessed soon
(e.g. Related data items (arrays) are usually stored together;
instructions are executed sequentially)

Cache
- The property of Locality of Reference makes the
Cache memory systems work
- Cache is a fast small capacity memory that should hold those information
which are most likely to be accessed

Main memory
CPU
Cache
memory
 Cache Memory

PERFORMANCE OF CACHE
Memory Access
All the memory accesses are directed first to Cache
If the word is in Cache; Access cache to provide it to CPU
If the word is not in Cache; Bring a block (or a line)
including
that word to replace a block now in Cache

- How can we know if the word that is required

is there ?
- If a new block is to replace one of the old blocks,
which one should we choose ?
Performance of Cache Memory System

Hit Ratio - % of memory accesses satisfied by Cache memory system

Te: Effective memory access time in Cache memory system
Tc: Cache access time
Tm: Main memory access time

Te = Tc + (1 - h) Tm

Example: Tc = 0.4 s, Tm = 1.2s, h = 0.85%

Te = 0.4 + (1 - 0.85) * 1.2 = 0.58s
 Cache Memory

MEMORY AND CACHE MAPPING - ASSOCIATIVE MAPPLING -

Mapping Function
Specification of correspondence between main
memory blocks and cache blocks
Associative mapping
Direct mapping
Set-associative mapping
Associative Mapping
- Any block location in Cache can store any block in memory
-> Most flexible
- Mapping Table is implemented in an associative memory
-> Fast, very Expensive
- Mapping Table
Stores both address and the content of the memory word
address (15 bits)

Argument register

Address Dat
01000 3a4 5 0
CAM 0277 671
7
2223 0
1234
5
 Cache Memory

MEMORY AND CACHE MAPPING - DIRECT MAPPING -

- Each memory block has only one place to load in Cache

- Mapping Table is made of RAM instead of CAM
- n-bit memory address consists of 2 parts; k bits of Index field
and
n-k bits of Tag field
- n-bit addresses are used to access main memory
Addressing and k-bit Index isTag(6)
used Index(9)
to access the Cache
Relationships
00 000 32K x 12
000
512 x 12
Main memory Cache memory
Address = 15 bits Address = 9
Data = 12 bits Data
777 bits = 12 bits
77 777
Direct Mapping Cache
OrganizationMemory Memory data
address
00000 1220 Cache memory
Inde
address
x Tag Data
00777 2340 000 00 1220
01000 3450

01777 4560
02000 5670

777 02 6710
02777 6710
 Cache Memory

DIRECT MAPPING
Operation

- CPU generates a memory request with (TAG;INDEX)

- Access Cache using INDEX ; (tag; data)
Compare TAG and tag
- If matches -> Hit
Provide Cache[INDEX](data) to CPU
- If not match -> Miss
M[tag;INDEX] <- Cache[INDEX](data)

Cache[INDEX] <- (TAG;M[TAG; INDEX])

CPU <- Cache[INDEX](data)
Direct Mapping with block size of 8
words Inde tag dat 6 6 3
x
000 01 3a4 5 0 Tag Block Word
Block 0
007 01 657
010 8 INDEX
Block 1
017

Block 63 77 0
0
77 2
0 671
7 2 0
 Cache Memory

MEMORY AND CACHE MAPPING - SET ASSOCIATIVE MAPPING -

- Each memory block has a set of locations in the Cache to

load
Set Associative Mapping Cache with set size of two
Index Tag Data Tag Data
000 01 3450 02 5670

777 02 6710 00 2340

Operation
- CPU generates a memory address(TAG; INDEX)
- Access Cache with INDEX, (Cache word = (tag 0, data 0); (tag 1, data
1))
- Compare TAG and tag 0 and then tag 1
- If tag i = TAG -> Hit, CPU <- data i
- If tag i  TAG -> Miss,
Replace either (tag 0, data 0) or (tag 1, data 1),
Assume (tag 0, data 0) is selected for replacement,
(Why (tag 0, data 0) instead of (tag 1, data 1) ?)
M[tag 0, INDEX] <- Cache[INDEX](data 0)
Cache[INDEX](tag 0, data 0) <- (TAG, M[TAG,INDEX]),
CPU <- Cache[INDEX](data 0)
 Cache Memory

BLOCK REPLACEMENT POLICY

Many different block replacement policies are available

LRU(Least Recently Used) is most easy to implement

Cache word = (tag 0, data 0, U0);(tag 1, data 1, U1), Ui = 0 or 1(binary)

Implementation of LRU in the Set Associative Mapping with set size = 2

Modifications

Initially all U0 = U1 = 1
When Hit to (tag 0, data 0, U0), U1 <- 1(least recently used)
(When Hit to (tag 1, data 1, U1), U0 <- 1(least recently used))
When Miss, find the least recently used one(Ui=1)
If U0 = 1, and U1 = 0, then replace (tag 0, data 0)
M[tag 0, INDEX] <- Cache[INDEX](data 0)
Cache[INDEX](tag 0, data 0, U0) <- (TAG,M[TAG,INDEX], 0); U1 <-
1
If U0 = 0, and U1 = 1, then replace (tag 1, data 1)
Similar to above; U0 <- 1
If U0 = U1 = 0, this condition does not exist
If U0 = U1 = 1, Both of them are candidates,
Take arbitrary selection
 Cache Memory

CACHE WRITE
Write Through
When writing into memory
If Hit, both Cache and memory is written in parallel
If Miss, Memory is written
For a read miss, missing block may be
overloaded onto a cache block
Memory is always updated
-> Important when CPU and DMA I/O are both executing
Slow, due to the memory access time
Write-Back (Copy-Back)
When writing into memory
If Hit, only Cache is written
If Miss, missing block is brought to Cache and write into Cache
For a read miss, candidate block must be
written back to the memory
Memory is not up-to-date, i.e., the same item in
Cache and memory may have different value
 Virtual Memory

VIRTUAL MEMORY
Give the programmer the illusion that the system has a very large memory,
even though the computer actually has a relatively small main memory

Address Space(Logical) and Memory

Space(Physical)
address space memory space

virtual address Mapping

physical address
(logical address)

address generated by programs actual main memory address

Address Mapping
Memory Mapping Table for Virtual Address -> Physical Address
Virtual address

Virtual Memory Main memory

addres addres Main
mapping memory
sregister tabl sregister
e

Physical
Address
Memory table Main memory
buffer register buffer register
 Virtual Memory

ADDRESS MAPPING
Address Space and Memory Space are each divided
into fixed size group of words called blocks or
pages
Page 0
Page 1
1K words group Page 2
Address Memory space Block 0
Page 3
space M = 4K = 212 Block 1
N = 8K = 213 Page 4
Block 2
Page 5
Block 3
Page 6
Page 7
Organization of memory Mapping Table in a paged system
Page Line number
no.
1 0 1 0 1 0 1 0 1 0 0 1 1 Virtual address

Table Presenc
addres bit
e
s 000 0 Main memory
001 11 1 Block 0
010 00 1 Block 1
011 0 01 0101010011 Block 2
100 0 Block 3
Main memory
101 01 1 address
Memory page 110 10 1 register
table 111 0 MBR

01 1
 Virtual Memory

ASSOCIATIVE MEMORY PAGE TABLE

Assume that
Number of Blocks in memory = m
Number of Pages in Virtual Address Space = n
Page Table
- Straight forward design -> n entry table in
memory
Inefficient storage space utilization
<- n-m entries of the table is empty

- More efficient method is m-entry Page Table

Page Table made of an Associative Memory
m words; (Page Number:Block Number)
Virtual address
Page no.
1 0 1 Line number Argument register

1 0 1 0 0 Key register

0 0 1 1 1
0 1 0 0 0 Associative memory
1 0 1 0 1
1 1 0 1 0
Page no.Block no.
Page Fault
Page number cannot be found in the Page
Table
 Virtual Memory

PAGE FAULT
3 Page is on backing
1. Trap to the OS store
O
2. Save the user registers and program state S

3. Determine that the interrupt was a page fault 2 trap

4. Check that the page reference was legal and
determine the location of the page on the
backing store(disk) 1 Referenc
5. Issue a read from the backing store to a free LOAD e
M 0
frame 6
restart
a. Wait in a queue for this device until serviced instruction 4
b. Wait for the device seek and/or latency time bring in
free
missing
c. Begin the transfer of the page to a free frame 5 pag
rese frame
6. While waiting, the CPU may be allocated to tpag e
some other process e
tabl
e
7. Interrupt from the backing store (I/O completed)
8. Save the registers and program state for the other user main memory
9. Determine that the interrupt was from the backing store
10. Correct the page tables (the desired page is now in memory)
11. Wait for the CPU to be allocated to this process again
12. Restore the user registers, program state, and new page table, then
resume the interrupted instruction.

Processor architecture should provide the ability

to restart any instruction after a page fault.
 Virtual Memory

PAGE REPLACEMENT
Decision on which page to displace to make room
for
an incoming page when no free frame is available
Modified page fault service
1. Find the location of the desired page on the backing store
routine
2. Find a free frame
- If there is a free frame, use it
- Otherwise, use a page-replacement algorithm to select a victim
frame
- Write the victim page to the backing store
3. Read the desired page into the (newly) free frame
valid
4. Restart the user process
frame / invalid swap
bit out
1 victi
p
mage
2 change to
f 0 v i invali victi
m 3
4 d swap
f v reset page
table for desired
new page page in
backing store
page table

physical memory
 Virtual Memory

PAGE REPLACEMENT ALGORITHMS

FIF Reference
O 7string
0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1
7 7 7 2 2 2 4 4 4 0 0 0 7 7 7
0 0 0 3 3 3 2 2 2 1 1 1 0 0
1 1 1 0 0 0 3 3 3 2 2 2 1
Page
frames

FIFO algorithm selects the page that has been in memory the longest
time
Using a-queue - every time a page is loaded, its
identification is inserted in the queue
Easy to implement
May result in a frequent page fault
Optimal Replacement (OPT) - Lowest page fault rate of all
algorithms
Replace that page which will not be used for the longest period of
time
Reference
7string
0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1
7 7 7 2 2 2 2 2 7
0 0 0 0 4 0 0 0
1 1 3 3 3 1 1
Page
frames
 Virtual Memory

PAGE REPLACEMENT ALGORITHMS

LRU
- OPT is difficult to implement since it requires future
knowledge
- LRU uses the recent past as an approximation of near future.
Replace that page which has not been
used for the longest period of time

Reference
7string
0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1
7 7 7 2 2 4 4 4 0 1 1 1
0 0 0 0 0 0 3 3 3 0 0
1 1 3 3 2 2 2 2 2 7
Page
frames

- LRU may require substantial hardware assistance

- The problem is to determine an order for the
frames
defined by the time of last use
 Virtual Memory

PAGE REPLACEMENT ALGORITHMS

LRU Implementation Methods
• Counters
- For each page table entry - time-of-use register
- Incremented for every memory reference
- Page with the smallest value in time-of-use register is
replaced
• Stack
- Stack of page numbers
- Whenever a page is referenced its page number is
removed from the stack and pushed on top
- Least recentlyReference
used page number is at the bottom
string
4 7 0 7 1 0 1 2 1 2 7 1 2

2 7
1 2
0 1
7 0
LRU Approximation 4 4

- Reference (or use) bit is used to approximate the LRU

- Turned on when the corresponding page is
referenced after its initial loading
- Additional reference bits may be used
 Memory Management Hardware

MEMORY MANAGEMENT HARDWARE

Basic Functions of MM
- Dynamic Storage Relocation - mapping logical
memory references to physical memory references
- Provision for Sharing common information stored
in memory by different users
- Protection of information against unauthorized
access
Segmentatio
n - A segment is a set of logically related instructions
or data elements associated with a given
name
- Variable size
User's view of memory
The user does not think of
Stack memory as a linear array
Subroutine of words. Rather the user
Symbol prefers to view memory as
Table
a collection of variable
SQRT
Main sized segments, with no
Program
necessary ordering among
segments.
User's view of a program
 Memory Management Hardware

SEGMENTATION
- A memory management scheme which supports
user's view of memory
- A logical address space is a collection of segments
- Each segment has a name and a length
- Address specify both the segment name and the
offset within the segment.
- For simplicity of implementations, segments are
numbered.
Segmentation Segment Table
Hardware
s

limi base
t
CPU (s,d)

Memory
y
< +
n

error
 Memory Management Hardware

SEGMENTATION EXAMPLE

1400
Subroutine Stac Segment
k
Segment 0
Segment 3 2400
0
Symbol
Table 3200

SQRT Segment Segment

4 3
Segment Main
Program 4300
1 Segment
Segment 2 4700
2
Segment
Logical Address Space
4
5700
6300
Segment
Segment Table 1 6700
limit
base 1400
0 1000
1 400 6300
2 400 4300
3 1100 3200
4 1000 4700
 Memory Management Hardware

SHARING OF SEGMENTS

Editor
limit 43062
base
0 25286
Segment 1 43062
4425 68348 Editor
0
Data 1 Segment Table
(User 1) 6834
Segment Data 1 8
7277
1 3
Logical Memory
(User 1)

90003
Data
2 9855
6
limit
Editor base
0 25286
1 43062
8550 90003 Physical Memory
Segment
0 Segment Table
Data (User 2)
2
Segment
1
Logical Memory
(User 2)
 Memory Management Hardware

SEGMENTED PAGE SYSTEM

Logical
address
Segmen Pag Word
t e

Segment Page
table table

Block Word
Physical
address
 Memory Management Hardware

IMPLEMENTATION OF PAGE AND SEGMENT TABLES

Implementation of the Page Table

- Hardware registers (if the page table is reasonably small)
- Main memory
- Page Table Base Register(PTBR) points to PT
- Two memory accesses are needed to access
a word; one for the page table, one for the
word
- Cache memory (TLB: Translation Lookaside Buffer)

- To speedup the effective memory access time,

a special small memory called associative
memory, or cache is used

Implementation of the Segment Table

Similar to the case of the page
table
 Memory Management Hardware

EXAMPLE
Logical and Physical Addresses
Logical address format: 16 segments of 256 pages
each, each page has 256words
4 8 8
Segment Page Word

20
2 x 32
Physical Physical address format: 4096 blocks of 256 words
memory each, each word has 32bits
12 8
Block Word

Logical and Physical Memory Address Assignment

Hexa
address Page number
60000 Page 0 Segment Page Block
60100 Page 1 6 00 012
6 01 000
60200 Page 2 6 02 019
6 03 053
60300 Page 3 6 04 A61
60400 Page 4
604FF
(a) Logical address assignment (b) Segment-page versus
memory block assignment
 Memory Management Hardware

LOGICAL TO PHYSICAL MEMORY MAPPING

Segment and page table Logical address (in
hexadecimal)
mapping 6 0 7E
2

Segment Page Physical memory

0 table 00 table 00000
Block 0
000FF
6 35 35 012
36 000
3 019 0120
0 Block 12
7
3 053 012FF
F A3 8
39 A61

01900 32-bit word

0197
A3 012 019FF
E

Associative memory
mapping Segment Page Block
6 02 019
6 04 A61
 Memory Management Hardware

MEMORY PROTECTION

Protection information can be included in the

segment table or segment register of the
memory
management hardware

- Format of a typical segment descriptor

Base address Length Protection

- The protection field in a segment descriptor specifies

the Access Rights to the particular segment

- In a segmented-page organization, each entry in the

page table may have its own protection field to
describe the Access Rights of each page
Full read and write privileges.
Read only (write protection)
- Access Rights:
Execute only (program
protection)
System only (O.S. Protection)
A Typical Cache and TLB Design
From CPU
translator
Virtual Real
Address Address Virtual Address
Page Line Word in To translator
Number Number Line
A
CPU Memory

Hash
Function Real Address Data
TLB
Cache

S S

Compare Virtual Real Compare Addresses

Addresses Address & Select Data
Data

Word Select & Align

To Main Memory
S = Select
Data
Out
Structure of Cache Entry and Cache Set

Real Address Tag Data Valid

Cache Entry

Entry 1 Entry 2  Entry E Replacement status

Cache Set
 Cache Operation Flow Chart

Receive Virtual Address

Hash Page Number Use Line Number

to Select Set
Search TLB
Read Out Address Tags
A
yes
In TLB ? Compare Addresses
no yes
Match ?
Send Virtual Address Update Replacement
to Translator Status in TLB no
Send Real Address
Update Replacement
to Main Memory
Status
Use Page & Segment tables
to Translate Address Select Receive Line from
Correct Main Memory
Line
Put in TLB Store Line
in Cache
Select Correct
Word from Line
A

Read Out
 Virtual Address Format - Example

Page number Byte within

page
Byte within
line

31 21 20 17 12 11 10 4 3 2 1 0

Byte within
Select set Select set word
in TLB in cache
Map through Word within
page directory Map through
page table Line number line

Virtual Address of Fairchild Clipper

References

• Text Books:
• Computer System Architecture M. M. Mano:, 3rd ed., Prentice Hall of India,
New Delhi, 1993.
• Computer Organization and Design: The Hardware/Software Interface, David
A. Patterson and John L. Hennessy.
• Computer Organization and Embedded Systems, Carl Hamacher.

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e-Mail: jayashree.e15737@cumail.in

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