Unit2 COD

COD-Unit-2
Bus Unit in micro processor/microcomputer
Address bus
Data bus
Control bus
Register transfer Language
• Information transfer from one register to
another is designated in symbolic
• form by means of a replacement operator. The
statement
• R2 R1
Register notation
Here P acts as control function,
The above statement may be written as
Register Transfer Language
Memory transfer
• Memory Read:
• CPU put address on address bus, [AR is address Register]
• activate control line [Memory read],
• data comes out of memory and kept on data bus and
transferred to CPU [DR is data Register]
Memory transfer
• Memory write:
• CPU put address on address bus,
• activate control line [Memory write],
• Put data on data bus and transferred to of memory
• The outputs of four registers, RO, Rl, R2. and R3, are connected through
4-to1-line multiplexer to the inputs of a fifth register, R4. Each register is
eight bits long. The required transfers are dictated by four timing variables
To through T3, as follows:
To: R5RO
T1: R5Rl
T2: R5R2
T3: R5R3
The timing variables are mutually exclusive, which means that only one
variable is equal to I at any given time, while the other three are equal to
0. Draw a block diagram showing the hardware Implementation of the
register transfers. Include the connections necessary from the four timing
variables to the selection inputs of the multiplexers and to the load input of
register R5.
Instruction set architecture
• Stored program organization
Opcode: tells operation to be performed
Address: gives address of operand, this may be used in
some operations like complement Accumulator, clear AC,
increment AC
Modified instruction format
Animation of sequence of operations for memory read
operation:
https://electro-nx.blogspot.com/2019/02/instruction-
fetch-in-microprocessor.html
Arithmetic micro operation
Binary adder
Binary adder/ subtractor circuit
Incrementer circuit
Arithmetic circuit:
Logical microoperatoins
Hardware Implementation
s2 s1 s0 output
0 0 0 AND
0 0 1 OR
0 1 0 X-OR
0 1 1 NOT
1 0 0 NAND
1 0 1 NOR
1 1 0 Left shift (upward )
1 1 1 Right shift (downward)
Shift micro operations
Ashr  shifts right with

sign bit LSB lost, sign bit
remains unchanged
Ashl shifts left with 0
inserted at LSB, sign may
rotate
change overflow
Arithmetic shift
Over flow detection

Hardware implementation
ALU Design
1 bit ALU;
For multiple bits, add in parallel
Register set
Bus Design for the register set
Instruction set completeness
Computer Instruction:
Memory reference instructions
Register reference Instruction
I/O operations:
Timing
and
Control
Logic
Instruction Cycle:
Fetch and Decode

To provide the data path fro AR PC we must use T0 signal to
get following:
During next clock pulse (T1):
Hence T1 is used to make following connection paths:

Instruction cycle
flow chart
CPU design
Register Reference Instruction:
https://www.youtube.com/watch?
v=q8PUsw-xvjs
Memory Reference Instruction:
AND to AC
ADD to AC
Load to AC
Store AC
Branch Unconditional
BSA: Branch and save return address
ISZ: Increment (Memory) and skip (next instruction) if
(incremented value) zero
Input output and Interrupt:
Output flag
Serial comm
Parallel comm
Serial comm
Parallel comm
Input flag
Input output instruction
Program Interrupt:
Due to inclusion of Interrupt cycle, we need to modify
the instruction cycle:
Complete
processor
design:
Control Logic of AR:
Hence different control inputs (

load, clear and increment) are:
Accumulator Logic development
D0T5:AC AC^DR
D1T5: AC AC+DR
D2T5: AC DR
rB11: AC0
rB9: AC AC’
rB7:------
rB6: ------
rB5: ACAC+1
pB11:AC(7-0)INPR LD(AC): D0T5+D1T5+D2T5+rB9+rB7+rB6+pB11
Clear(AC): rB11
INR(AC): rB5
Micro-Programmed control Unit
Hard-wired control Unit Micro-programmed control Unit

Micro-programmed control unit organization:
Detailed micro-
programmed control
Unit
Instruction Mapping:
Micro-instruction format
Stack Organization:
Initially:
SP=0;
EMPTY=1;
FULL=0;
PUSH:
PULL:
Computer
memory
Application of Stack pointer:
Evaluation of mathematical expression:
Infix
Prefix Postfix (Reverse) notation
notation
notation (RPN)
A+B
+AB AB+
e.g.
e.g. e.g.
A*B+C*D
*+AB+CD AB*CD*+
Most suitable with Stack
pointer (LIFO)
(A+B)*[C*(D+E)+F]
RPN: AB+CDE+*F+*
3*4+5*6
Convert into RPN: 34*56*+
Push 3, push 4 multiply
push 5 push 6 multiply add
End of Unit 2

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COD-Unit-2

Bus Unit in micro processor/microcomputer

Ashr  shifts right with

Over flow detection

Fetch and Decode

During next clock pulse (T1):

Hence T1 is used to make following connection paths:

Hence different control inputs (

Hard-wired control Unit Micro-programmed control Unit

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