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FPGA Architecture

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71 views20 pages

FPGA Architecture

Uploaded by

Guru Prasath
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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FPGA

ARCHITECTURE
Field Programmable Gate
Array
● (FPGA)
FPGA was introduced in 1985 by xilinx.
● It has very high logic capacity and consists of an array of
programmable logic blocks surrounded by programmable
interconnects.
● It can be configured by end-users to implement specific
applications.
● It can capacity up to multi-millions logic gates and speed up to 500 MHz
FPGA
● Early FPGAs
ARCHITECTURE
N x N array of unit cells (CLB + routing) ,Special routing along
center axis
● Next Generation FPGAs
M x N unit cells , Small block RAMs around edges
● More recent FPGAs
Added block RAM arrays , Added multiplier cores , Adders
processor cores
● Special Functions
Internal SRAM , Embedded Multipliers, DSP blocks, logic
analyzer,CPUs , High speed I/O (~10GHz), DDR/DDRII/DDRIII
SDRAM interfaces
FPGA
ARCHITECTURE
There are three primary configurable
elements in FPGA:
● Configurable Logic Block
(CLB): It implement different
functions.
● Input/Output Block (IOB) : It
provides the interface between
external pins and internal signal
lines.
● Programmable Routing
channel
: It controls the connections.
CONFIGURABLE LOGIC
BLOCK(CLB)
● Repeating logic source in FPGA
● Components in CLB executes complex logic function, implement
memory function and synchronize code on FPGA
● CLBs contain smaller components like,
❏ Flip flops
❏ Look up tables(LUT)
❏ Multiplexers
● Allows user to implement any logical function within chip
● It provides basic computations and storage element used in digital
system
IMPLEMENTED IN CONFIGURABLE
N- INPUT LOOK UP LOGIC BLOCK
TABLE
CLB contd..
● Each CLB contains two basic
structures called Slice
● Each basic Slice contains 4
look-up tables, 4 storage units, a
wide function multiplexer, and
carry logic
● This basic structure (Slice) is
called SLICEL.
● Besides, some Slice also includes
using RAM to store data and the
function of shifting using 32-bit
registers.
● The basic structure that supports
these functions is called SLICEM.
CLB EXAMPLES
XILINX LOGIC BLOCK
● A SRAM function as LUT
● Address line of SRAM as input and Output of SRAM gives logic output
ACTEL LOGIC BLOCK
● Consist of multiple number of multiplexers and logic gates
● If input of multiplexer are connected to constant or to a signal, it can be
used to implement different logic functions.
ALTERA - LUT [Alter “Flex”, Altera “Max”]
QUICKLOGIC - LUT
ATMEL - Multiplexers and basic gates
CLB EXAMPLES

● Artix - 7

SLICEL
Four 6- input
LUT
Eight D- Flip
flops
Adders
MUXs
INPUT / OUTPUT BLOCK
(IOB)
• Two types of IOBS are there
a. Dedicated for configuration of FPGA
b. User Configurable
• Input/output (I/O) Block is used to bring
signals onto the chip and send them back off
again.
• An i/o pin in the input/output block can be used
for input,output and both.
• The input and output paths contain edge
triggered D flip flops. They are selectable by
multiplexers.
An input/output block (IOB) for a field programmable
gate array (FPGA) device includes:

(a)an input for receiving.


(b)a delay element, coupled to the input.
(c)a first multiplexer, coupled to the delay element.
(d)a second multiplexer, coupled to the first multiplexer.
(e)a register/latch, coupled to the second multiplexer.
(f)a set/reset line for providing a set/reset signal.
(g)a decoder, coupled to the set/reset line.
(h)a third multiplexer, coupled to the register/latch
output.
(i)an amplifier, coupled to the third multiplexer.
Programmable
Interconnect
• Interconnect: Programmable Network of Signal
pathways between the inputs and outputs of functional
elements within the FPGA, such as IOBs, CLBs

• Interconnect is also called as


Routing.
• There are four kinds of
interconnect:
• Long
• Lines
Hex
• Lines
Double
• Lines
Direct
Lines
Programmable Switch Matrix
(PSM)
• Connects to
the
different kinds
of
interconnects across
the
device
.
• An interconnect tile
is
defined as a
single
switch
matrix
connected to
a
functional
element,
such as a CLB,
IOB.
Long
Lines
• Each set has 24 lines.
• Spans the die both horizontally and vertically.
• Connects to 1-out-of-6 interconnect tiles.
• Has low capacitance, thus these are well-suited
for carrying high frequency signals.
• Has minimum loading effects.
Hex
Lines
• Each set has 8 Hex lines.
• Spans the die both horizontally and vertically.
• Connects to 1-out-of-3 interconnect tiles.
• Between any given interconnect tile, there will
be
32 hex lines available.
• Driven only from one end of the route.
Double
Lines
• Each set has 8 Double lines.
• Spans the die both horizontally and vertically
in all four directions.
• Between any given interconnect tile, there will
be
32 Double lines available.
• Double lines ------ More Flexibile.
Direct
Lines
• Routes signals to Neighbouring tiles.
• Spans the die both horizontally, vertically
and Diagonally.
• Drives a signal from Sources tile to a double,
hex, and
line or long
conversely from the longer interconnect back
to line accessing a Destination
a direct
tile.
Advantages of
FPGA
● Small development overhead.
● Shorter design cycle.
● No NRE(non-recurring
engineering)costs.
● Quick time to market.
● No manufacturing delay.
● Reprogrammable.
● FPGAs reduce inventory.
Disadvantages of
FPGA
● Least efficient use of silicon/wiring resources.
● Limited size options
● Limited performance
● Not good for high volume applications
● If used for prototyping,still may have significant
changes when migrate to higher performance design
and package solution

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