Module – 2

8051 Instruction Set

 Module -2
8051 Instruction Set: Addressing Modes,
Data Transfer Instructions, Logical
Instructions, Arithmetic Instructions, Jump
& Call Instruction, 8051 stack, Stack and
subroutine instructions.
RBT: L1,L2
 General syntax for 8051 assembly language is as follows.
• LABEL: OPCODE OPERAND ; COMMENT
• LABEL: (THIS IS NOT NECESSARY UNLESS THAT SPECIFIC LINE
HAS TO BE ADDRESSED). The label is a symbolic address for the
instruction. When the program is assembled, the label will be given specific
address in which that instruction is stored. Unless that specific line of
instruction is needed by a branching instruction in the program, it is not
necessary to label that line.
• OPCODE: Opcode is the symbolic representation of the operation. The
assembler converts the opcode to a unique binary code (machine language).
• OPERAND: While opcode specifies what operation to perform, operand
specifies where to perform that action. The operand field generally contains
the source and destination of the data. In some cases only source or
destination will be available instead of both. The operand will be either
address of the data, or data itself.
• COMMENT: Always comment will begin with ; or // symbol. To improve
the program quality, programmer may always use comments in the
program.
 Addressing Modes

• The CPU can access data in various ways,

which are called addressing modes
Immediate Addressing Mode
• The source operand is a constant
• The immediate data must be preceded by the pound sign, “#”
• Can load information into any registers, including 16-bit DPTR
register
• DPTR can also be accessed as two 8-bit registers, the high
byte DPH and low byte DPL
• We can use EQU directive to access immediate
data

• We can use EQU directive to access immediate

data
 Register Addressing Mode
 Use registers to hold the data to be manipulated

 The source and destination registers must match in size

MOV DPTR, A will give an error

 The movement of data between Rn registers is not allowed

MOV R4,R7 is invalid
Accessing Memory- Direct Addressing Mode
 It is most often used, the direct addressing mode, to
access RAM locations 30H – 7FH
o The entire 128 bytes of RAM can be accessed
o The register bank locations are accessed by the
register names
Accessing Memory- Stack and Direct Addressing
Mode
 Only direct addressing mode is allowed for pushing or
popping the stack
• PUSH A is invalid
• Pushing the accumulator onto the stack must be coded as
PUSH 0E0H
Accessing Memory- Register-Indirect Addressing Mode
 A register is used as a pointer to the data
• Only register R0 and R1 are used for this purpose
• R2 – R7 cannot be used to hold the address of an operand
located in RAM
 When R0 and R1 hold the addresses of RAM locations, they
must be preceded by the “@” sign
 The advantage is that it makes accessing data dynamic
rather than static as in direct addressing mode
• Looping is not possible in direct addressing mode
 R0 and R1 are the only registers that can be used for pointers in
register indirect addressing mode

 Since R0 and R1 are 8 bits wide, their use is limited to access any
information in the internal RAM
 Whether accessing externally connected RAM or on-chip ROM,
we need 16-bit pointer
• In such case, the DPTR register is used.
 Indexed addressing mode is widely used in accessing data elements
of look-up table entries located in the program ROM.
 The look-up table allows access to elements of a frequently used table
with minimum operations
 The instruction used for this purpose is MOVC A,@A+DPTR
• Use instruction MOVC, “C” means code
• The contents of A are added to the 16-bit register DPTR to form
the 16-bit address of the needed data
Data Transfer instructions
 The MOV opcodes involve data transfers within the following
four distinct physical parts of 8051 memory :
• Internal RAM
• Internal special. function registers
• External RAM
• Internal and external ROM
 Finally, the following five types of opcodes are used to move
data:
• MOV
• MOVX
• MOVC
• PUSH and POP
• XCH
Data Transfer using immediate and register addressing modes

 A data MOV does not alter the contents of the data source
address.
 A copy of the data is made from the source and moved to the
destination address.
 The contents of the destination address are replaced by the
source address contents.
 It is impossible to have immediate data as a destination.
 All numbers must start with a decimal number (0-9), or the
assembler assumes the number is a label.
 Register-to-register moves using the register addressing
mode occur between registers A and RO to R7.
Data Transfer using direct, immediate and
register addressing modes
Data Transfer - External Data Moves
Data Transfer - Code Memory Read-Only
Data Moves
Data Transfer - External Data Moves
Data Transfer - Data Exchanges
 Arithmetic instructions
• The 8051 can perform addition, subtraction. Multiplication and division
operations on 8 bit numbers. The 24 arithmetic opcodes are grouped into as
follows
Arithmetic instructions - Addition
 All addition is done with the A register as the destination of
the result.
 All addressing modes may be used for the source: an
immediate number, a register, a direct address, and an indirect
address.
 Some instructions include the carry flag as an additional
source of a single bit that is included in the operation at the least
significant bit position
 ADD A, source; A = A + source
These instructions affect 3 bits in PSW:
• C = 1 if result of add is greater than FF
• AC = 1 if there is a carry out of bit 3
• OV = 1 if there is a carry out of bit 7, but not from bit 6, or
vice versa.
Addition of Unsigned Numbers
ADD A, source; A = A + source
 The instruction ADD is used to add two operands
 Destination operand is always in register A
 Source operand can be a register, immediate data, or in
memory
 Memory-to-memory arithmetic operations are never allowed
in 8051 Assembly language
 ADDC and Addition of 16-Bit Numbers
 When adding two 16-bit data operands, the propagation of
a carry from lower byte to higher byte is concerned
BCD Number System
The binary representation of the digits 0 to 9 is called BCD (Binary Coded
Decimal)
Unpacked BCD
 In unpacked BCD, the lower 4 bits of the number represent the BCD
number, and the rest of the bits are 0
• Ex. 00001001 and 00000101 are unpacked BCD for 9 and 5

Packed BCD
 In packed BCD, a single byte has two BCD number in it, one in the lower
4 bits, and one in the upper 4 bits
• Ex. 0101 1001 is packed BCD for 59H
 Adding two BCD numbers must give a BCD result

DA Instruction
 DA A ;decimal adjust for addition
 The DA instruction is provided to correct the aforementioned
problem associated with BCD addition
 The DA instruction will add 6 to the lower nibble or higher
nibble if need
Subtraction of Unsigned Numbers
 In many microprocessor there are two different instructions for
subtraction:

SUB and SUBB (subtract with borrow)

 In the 8051 we have only SUBB
 The 8051 uses adder circuitry to perform the subtraction

SUBB A, source ; A = A – Source – CY

 To make SUB out of SUBB, we have to make CY=0 prior to the
execution of the instruction
 Notice that we use the CY flag for the borrow

SUBB when CY = 0
 Take the 2’s complement of the subtrahend (source operand)
 Add it to the minuend (A)
 Invert the carry
Multiplication of Unsigned Numbers
The 8051 supports byte by byte multiplication only
 The byte are assumed to be unsigned data
MUL AB; A*B, 16-bit result in B, A
Division of Unsigned Numbers
The 8051 supports byte over byte division only
 The byte are assumed to be unsigned data
DIV AB ; A/B, Result(R, Q) in B, A
 Logical instructions
ANL destination, source ; dest = dest AND source
 This instruction will perform a logic AND on the two
operands and place the result in the destination
• The destination is normally the accumulator
• The source operand can be a register, in memory, or immediate
ORL destination, source; dest = dest OR source
 This instruction will perform a logic OR on the two operands
and place the result in the destination
• The destination is normally the accumulator
• The source operand can be a register, in memory, or immediate
XRL destination, source; dest = dest XOR source
 This instruction will perform a logic XOR on the two
operands and place the result in the destination
• The destination is normally the accumulator
• The source operand can be a register, in memory, or immediate
CPL A ; complements the register A
This is called 1’s complement
 Source and destination both will be the accumulator
 Content of A will 1’s complemented and stored back
in A itself.

 To get the 2’s complement, all we have to do is to

add 1 to the 1’s complement
CJNE destination, source, Label
 The actions of comparing and jumping are combined into a single
instruction called CJNE (compare and jump if not equal)
 The CJNE instruction compares two operands, and jumps if they are
not equal
 The destination operand can be in the accumulator or in one of the Rn
registers
 The source operand can be in a register, in memory, or immediate
• The operands themselves remain unchanged
 It changes the CY flag to indicate if the destination operand is larger
or smaller.
 Notice in the CJNE instruction that any Rn register can be compared
with an immediate value
 There is no need for register A to be involved
 The compare instruction is really a subtraction, except that the
operands remain unchanged
 Flags are changed according to the execution of the SUBB
instruction.
RR A ; rotate right A
In rotate right
 The 8 bits of the accumulator are rotated right one bit, and
 Bit D0 exits from the LSB and enters into MSB, D7
RL A ; rotate left A
In rotate left
 The 8 bits of the accumulator are rotated left one bit, and
 Bit D7 exits from the MSB and enters into LSB, D0
SWAP A
It swaps the lower nibble and the higher nibble
 In other words, the lower 4 bits are put into the
higher 4 bits and the higher 4 bits are put into the lower
4 bits
 SWAP works only on the accumulator (A)
Branch instructions
 Repeating a sequence of instructions a certain number of
times is called a loop.
 Loop action is performed by DJNZ reg, Label
• The register is decremented by one
• If it is not zero, it jumps to the target address referred to
by the label
• Prior to the start of loop the register is loaded with the
counter for the number of repetitions
• Counter can be R0 – R7 or RAM location
Branch instructions – Nested loop
If we want to repeat an action more times than 256, we
use a loop inside a loop, which is called nested loop.
 We use multiple registers to hold the count
Conditional Jumps
JZ label ; jump if A=0
Jump only if a certain condition is met.

JNC label ; jump if no carry, CY=0

 If CY = 0, the CPU starts to fetch and execute
instruction from the address of the label
 If CY = 1, it will not jump but will execute the next
instruction below JNC
Unconditional Jumps
 The unconditional jump is a jump in which control is
transferred unconditionally to the target location.
 Unconditional jumps do not test any bit or byte to determine
whether the jump should be taken.
 The jump is always taken.

LJMP (long jump)

• 3-byte instruction
• First byte is the opcode
• Second and third bytes represent the 16-bit target address (Any
memory location from 0000 to FFFFH)
SJMP (short jump)
• 2-byte instruction
• First byte is the opcode
• Second byte is the relative target address
• 00 to FFh (forward +127 and backward -128 bytes from the current
PC)

Calculating Short Jump Address

 To calculate the target address of a short jump (SJMP, JNC, JZ,
DJNZ, etc.)
• The second byte is added to the PC of the instruction immediately
below the jump
 If the target address is more than -128 to +127 bytes from the
address below the short jump instruction
• The assembler will generate an error stating the jump is out of range
Bit manipulation instructions
Bit manipulation instructions will check the conditions of the bit
and if condition is true, it jumps to the address specified in the
instruction. All the bit jumps are relative jumps.
Instructions that are used for signal-bit operations are
 8051 Stack Programming
• 8051 Stack
• The stack is a section of RAM used by the CPU to store
information temporarily.
• This information could be data or an address.
• The register used to access the stack is called the SP
(stack pointer) register.
• The stack pointer in the 8051 is only 8 bit wide, which
means that it can take value of 00 to FFH.
• When the 8051 is powered up, the SP register contains
value 07.
• RAM location 08 is the first location begin used for the
stack by the 8051.
• The storing of a CPU register in the stack is called
a PUSH
• SP is pointing to the last used location of the
stack
• As we push data onto the stack, the SP is
incremented by one
• This is different from many microprocessors
• Loading the contents of the stack back into a
CPU register is called a POP
• With every pop, the top byte of the stack is
copied to the register specified by the instruction
and the stack pointer is decremented once
• The CPU also uses the stack to save the address of the
instruction just below the CALL instruction
• This is how the CPU knows where to resume when it returns
from the called subroutine.
• The reason of incrementing SP after push is
• Make sure that the stack is growing toward RAM location 7FH,
from lower to upper addresses.
• If the stack pointer were decremented after push
• We would be using RAM locations 7, 6, 5, etc. which belong to
R7 to R0 of bank 0, the default register bank.
• When 8051 is powered up, register bank 1 and the stack are
using the same memory space
• We can reallocate another section of RAM to the stack.
• Stack and Subroutine instructions
• CALLs and Subroutines
•  Call instruction is used to call subroutine
• o Subroutines are often used to perform tasks that need to be performed
frequently
• o This makes a program more structured in addition to saving memory
space
•  LCALL (long call)
• o 3-byte instruction
• o First byte is the opcode
• o Second and third bytes are used for address of target subroutine
• • Subroutine is located anywhere within 64K byte address space
•  ACALL (absolute call)
• o 2-byte instruction
• o 11 bits are used for address within 2K-byte range
• 
• When a subroutine is called, control is transferred to
that subroutine, the processor
• o Saves on the stack the address of the instruction
immediately below the LCALL
• o Begins to fetch instructions from the new location
•  After finishing execution of the subroutine
• o The instruction RET transfers control back to the
caller
• • Every subroutine needs RET as the last instruction