Verilog Basic Concepts

CHAPTER -II
Basic Constructs
I. Syntax
• Verilog HDL is a case-sensitive language. All keywords are in lowercase.
1. Whitespace
2. Comments
3. Operators
4. Number Specification
5. Strings
6. Identifiers and Keywords
1. Whitespace
• Blank spaces (\b) , tabs (\t) and newlines (\n) comprise the
whitespace.
• Not ignored in strings
2. Comments
Two types:
1. single-line comment.
2. multi-line comment.
Ex: 1. // single line comment
2. /* this is a multiple line comment */

/* this is /* an illegal */ comment*/

/* This is // a legal comment */
3. Operators
• Operators are of three types, unary, binary, and ternary.
• Unary operators precede the operand.
• Binary operators appear between two operands.
• Ternary operators have two separate operators that separate three
operands.
Example:
a = - b; // - is a unary operator. b is the operand
a = b && c; // && is a binary operator. b and c are operands
a = b ? c : d; // ?: is a ternary operator. b, c and d are
operands
Number Specification
Two Types : 1. Sized
2. Unsized
1. Sized Numbers:
Syntax:<size>'<baseformat><number>
Example:
4’b1111 // this is a 4-bit binary number
12’habc // this is a 12-bit hexadecimal number
16’d225 // this is a 16-bit decimal number
12’h13x // this is a 12-bit hexadecimal number
2. Un-Sized Numbers:
Syntax: '<baseformat><number>
Example:
’b1111 // this is a 32-bit binary number
’O21 // this is a 32-bit Octal number
’d225 // this is a 32-bit decimal number
’h13x // this is a 32-bit hexadecimal number
X or Z values
• Verilog has two symbols for unknown and high impedance values.
• These values are very important for modeling real circuits.
• An unknown value is denoted by an X. A high impedance value is denoted by z
12'h13x // This is a 12-bit hex number; 4 least significant bits unknown
6'hx // This is a 6-bit hex number
32'bz // This is a 32-bit high impedance number
Negative numbers:
• Negative numbers can be specified by putting a minus sign before
the size for a constant number.
• Size constants are always positive.
• It is illegal to have a minus sign between <base format> and
<number>.
-6’d3[Correct] 4’d-2[Wrong]

Underscore Character:
Ex: 12’b1111_0000_1010

Question Mark:
‘?’ is the same as ‘z’ (only regarding numbers)
EX: 4’b10?? //the same as 4’b10zz
5. Strings
• A string is a sequence of characters that are enclosed by double quotes.
• Group of chars within double quotes.
• Do not embed newlines.
• It can’t be on multiple lines.
• You can use escaped characters (such as \t and \n) in strings.
Examples:
“Hello Verilog World” // is a string
“a /b ” //is a string
6. Identifiers & Keywords
• Keywords are special identifiers reserved to define the language
constructs.
• Special identifiers , language constructs.
• Lowercase.
• Keywords != identifiers.

Example: output OR; //output=keyword,

//OR = identifier.
II. Data Types
Value Set
Value Level Condition in Hardware Circuits
0 Logic zero, false condition
1 Logic one, true condition
X Unknown value
z High impedance, floating state

Two basic data Types

1. Net data types
2. Register data types
1. Net Data Types
• Nets represent connections between hardware
elements.
• In Fig, net a is connected to the output of and gate gl.
Net a will continuously assume the value computed at
the output of gate gl, which is b & C.
• The default value of a net is z
• Except the tri reg net, which defaults to X.
• Nets get the output value of their drivers.
Note : Net is not a keyword but represents a class of data types
such as wire, wand,wor, tri, triand, trior, trireg, etc.
wire, tri // For standard interconnection wires (default)

supply1, supply0 // For power or ground rails

wor, trior // For multiple drivers that are Wire-Ored

wand, triand // For multiple drivers that are Wire-ANDed

tri1, tri0 //For nets that pull up or down when not driven

• Note: tri0 and tri1 are non-synthesizable net types.

Syntax:
net_type [range] list_of_variables;
Examples:
wand w; // A scalar net of type "wand"
tri [15:0] bus; // A 16-bit three-state bus
wire [0:31] w1, w2; // Two 32-bit wires with msb = bit 0
wire #5 addr_sel; // A scalar wire with a delay
2. Registers or Variable
• Registers represent data storage elements. Registers retain value until
another value is placed onto them.
• In Verilog, the term register merely means a variable that can hold a
value. Unlike a net, a register does not need a driver.
• Values of registers can be changed anytime in a simulation by assigning a
new value to the register.
• Register data types are commonly declared by the keyword reg. The
default value for a reg data type is X.
• integer // Signed 32-bit integer variable
• real // (64-bit)Signed double precision floating-point variable
• reg // Unsigned storage of varying bit width
• time // Unsigned 64-bit integer variable
• Realtime // is of type real used for storing time as a floating point
value.
 Syntax:
integer list_of_register_variables;
real list_of_variables;
reg [range] list_of_register_variables;
time list_of_register_variables;

EXAMPLE:
• reg [3:0] v; // A 4-bit vector reg
• reg [1:8] m,n; // Two 8-bit reg’s
3.Vectors
• Nets or reg data types can be declared as vectors (multiple bit widths). If
bit width is not specified, the default is scalar (l-bit).
Example:
wire a; // scalar net variable, default
wire [7:0] bus; // 8-bit bus
wire [31:0] busA,busB,busC; // 3 buses of 32-bit width.
reg clock; // scalar register, default
4.Integer
• Integers are declared by the keyword integer.
• The default width for an integer is the host-machine word size, which is
implementation specific but is at least 32 bits.
• Registers declared as data type reg store values as unsigned quantities,
whereas integers store values as signed quantities.
Example:
integer counter; // general purpose variable used as a
counter.
initial
counter = -1; // A negative one is stored in
the counter
5.Real
• Real number constants and real register data types are declared with the
keyword real.
• They can be specified in decimal notation (e.g., 3.14) or in scientific
notation (e.g., 3e6, which is 3 X 106 ).
• Real numbers cannot have a range declaration, and their default value is
0.
Example:
real delta; // Define a real variable called delta
initial begin
delta = 4e10; // delta is assigned in
scientific notation
delta = 2.13; // delta is assigned a value
end
integer i; // Define an integer i
initial i = delta; // i gets the value 2 (rounded value of 2.13)
6.Time
• Verilog simulation is done with respect to simulation time
• A special time register data type is used in Verilog to store simulation
time.
• A time variable is declared with the keyword time.
• The width for time register data types is implementation specific but is
at least 64 bits
• Can use $time system task
• Simulation time is measured in terms of simulation seconds. The unit is
denoted by S, the same as real time.
EX: time chng_hist[1:1000] // an array of 1000 time values
7.Arrays
• Arrays are allowed in Verilog for reg, integer, time, and vector register
data types.
• Arrays are not allowed for real variables.
• Multidimensional arrays are not permitted in Verilog.
Note: It is important not to confuse arrays with net or register vectors. A
vector is a single element that is n-bits wide. On the other hand, arrays
are multiple elements that are l-bit or n-bits wide
Syntax:
<data_type> <var_name>[start_index : end_index];
Examples:
• integer count[0:7]; // An array of 8 count variables
• reg bool[31:0]; // Array of 32 one-bit boolean register
variables
• time chk_point[1:100]; // Array of 100 time checkpoint
variables
• reg [4:0] port_id[0:7]; // Array of 8 port_ids; each port_id is 5
bits wide
• wire [7:0] w_array2 [5:0]; // Declare an array of 8 bit vector
wire
8.Memories
• Memories are modeled in Verilog simply as an array of registers.
one-8-bit memory 8-one bit memory

reg [7:0]mem;

reg mem[0:7];
Examples:

reg mem1bit[0:1023]; // Memory mem1bit with 1K 1-bit words

reg [7:0] membyte[0:1023]; // Memory membyte with 1K 8-bit

words(bytes)

memory size :256 and each can store 4 bit of data

Reg [3:0] mem [0:255];

9.Parameters
• Parameter values for each module instance can be overridden
individually at compile time.
• This allows the module instances to be customized.
• Parameters cannot be used as variables
• Parameters can be changed at module instantiation or by using the
defparam statement
Examples
parameter port-id = 5; //Defines a constant port-id
 10.Strings
• Strings can be stored in reg.
• The width of the register variables must be large enough to hold the
string.
Example
reg [8*18:1] string-value; //Declare a variable that is l8
bytes wide initial
string-value = "HelloVerilogWorld"; // String can be
stored in variable
III. System Tasks

• $display, $monitor, $strobe, $write

• $finish, $stop

• $time , $real time

1.Displaying Information
 $display is the main system task for displaying values of
variables or strings or expressions.
 Example: $display("Hello Verilog World");
Format Display
%d or %D Display variable in decimal
%b or %B Display variable in binary
%S or %S Display string
%h or %H Display variable in hex
%c or %C Display ASCII character
%m or %M Display hierarchical name (no
argument required)
%v or %V Display strength
%o or %O Display variable in octal
%t or %T Display in current time format
%e or %E Display real number in scientific
format (e.g.,3e10)
%f or %F Display real number in decimal format
(e.g., 2.13)
%g or %G Display real number in scientific or
decimaI, whichever is shorter
Examples:
1. $display(“Hello Verilog World!”);
Output: Hello Verilog World!
2. $display($time);
Output: 230
3. reg [0:40] virtual_addr;
$display(“At time %d virtual address is %h”, $time,
virtual_addr);
Output: At time 200 virtual address is 1fe000001c
2. Monitoring Information
• $monitor continuously monitors the values of the variables or signals
specified in the parameter list and displays all parameters in the list
whenever the value of any one variable or signal changes
• if there is more than one $monitor statement in your simulation, the last
$monitor statement will be the active statement.
• The earlier $monitor statements will be overridden.
Example:
initial
begin
$monitor($time, “Value of signals clock=%b, reset=%b”,
clock, reset);
End
Output:
0 Value of signals clock=0, reset=1
5 Value of signals clock=1, reset=1
10 Value of signals clock=0, reset=0
3. Stopping and finishing in a simulation
• The task $stop is provided to stop during a simulation.
• The $stop task is used whenever the designer wants to suspend the
simulation and examine the values of signals in the design.
• The $finish task terminates the simulation.
Example:
initial
begin
clock=0;
reset=1;
#100 $stop;
#900 $finish;
end
IV. Compiler Directives
• All compiler directives start with an accent grave (`), also called a “back-
tick”.
Most Commonly Used are:

• `include is used to insert the contents of a source code file.

• `timescale is used to establish a simulation timescale.

• `define is used to define a text replacement macro.

1.‘define
• The 'define directive is used to define text macros in Verilog
2. ‘include
• The ‘include directive allows you to include entire contents
of a Verilog source file in another Verilog file during
compilation
• This directive is typically used to include header files, which
typically contain global or commonly used definitions
3 . ‘timescale
• The specifies the unit of measurement for times and delays.
The specifies the precision to which the delays are rounded
off during simulation
`include compiler directive.
Syntax:
`include “<filename>”
EX: `include “module_dut.v”
`timescale compiler directive.
Syntax:
`timescale time_units / precision_units
EX : `timescale 1ns/1ps
`define
Syntax:
`define <macro_name> <macro_text>
EX: `define A_WIDTH 4
`define D_WIDTH 32
Conditional Compilation Directives:
• Verilog has following conditional compiler directives.
• `ifdef `else `elsif and `endif
• `ifndef, `else, `elsif, and `endif

`ifdef Syntax :
`ifdef <text_macro_identifier>

ifdef_group_of_lines
`elsif <text_macro_identifier>

elsif_group_of_lines
`else
else_group_of_lines
`endif
• The `ifdef compiler directive checks for the definition of a text_macro_name.
• If the text_macro_name is defined, then the lines following the `ifdef directive
are included.
• If the text_macro_name is not defined and an `else directive exists, then this
source is
compiled.
• Ex: module switches();

initial
begin
`ifdef TYPE_1

$display(" TYPE_1 message ");

`else`if TYPE_2

$display(" TYPE_2 message ");

`else
$display(" else_message ");
`endif
end
endmodule
Example:
`define and_gate
module and_op (a, b, c);
output reg a;
input b,c;

initial begin
`ifdef and_gate // use `ifndef also here
assign a = b & c;
$display("and output a= %0b",a);
`else
assign a = b ^ c;
$display("xor output a= %0b",a);
`endif
end
endmodule
Module Parameters
1. parameter
2. localparam

• Localparam – protect the value from out side and local to

module.
• Parameter – can be changed or redefined from outer
module/called module.
Parameters

Syntax : parameter list_of_assignments;

Examples:
parameter cycle = 20;
parameter prop_del = 3;
parameter setup = cycle/2 -
prop_del;
parameter width = 8;
parameter x_word = 16’bx;
Module Parameters

module mod1(out,in1,in2); module mod1(out,in1,in2);

... ...
parameter cycle = 8, localparam cycle = 8,
Data_width= 32, Data_width= 32,
addr_width= 15; addr_width= 15;
… …
reg [Data_width-1:0]; reg [Data_width-1:0];
Wire[addr_width-1:0] Wire[addr_width-1:0]
endmodule endmodule
Overriding Module Parameters

module mod1(out,in1,in2); module test;

... ...

parameter cycle = 8, mod1 I1 (out,in1,in2);

real_constant = defparam I1.cycle = 6;

2.039, defparam l1.x_word =

x_word = 16’bx; 16’b0;

… ...

endmodule endmodule
Contd.

module
mod1(out,in1,in2); module top;
... ...
parameter cycle = 8; mod1 #(6,3.1,16’bx) dut
parameter real_constant (out,in1,in2);
= 2.039; ...
parameter x_word = endmodule
16’bx;
...
endmodule
VII. Synthesizable and Non-
Synthesizable Constructs
• If a piece of HDL can be converted to a design with logic gates
by a synthesis tool, then it is synthesizable.
• If a piece of HDL is used for creating reference events, trackers,
displays, file dumping, etc., and the synthesis tool cannot infer a
digital circuit, then it is non-synthesizable
Specify Blocks
• The specify blocks describe module timing checks and pin to
pin timing in Verilog.
• The timing checks include predefined systems tasks like
$setup, $hold, $width, $period, $skew, $recovery,
$setuphold
• The timing checks are done on the events on nets and regs
with the goal of checking the time between two events on
two signals or between two events on the same signal.
Specify Blocks – Syntax
specify
{ specify_item}
endspecify
module dff_dut (clk,rst,d,q);
input d,clk,rst;
output reg q;

always @(posedge clk or posedge rst)

begin
if(rst) q<=0;
else q<=d;
end

specify
specparam S_VALUE = 3;
specparam H_VALUE = 10;

(clk => q) = (S_VALUE, H_VALUE);

$setup(d,posedge clk,S_VALUE);
$hold(posedge clk,d,H_VALUE);
endspecify

endmodule
THANK YOU
• Add code and output snippets for all data types
• Code snippet and output for system tasks and compiler directives
• Code snippet and output for parameters and defines