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10.test - 2024

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9 views12 pages

10.test - 2024

Uploaded by

abhiwork11111
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Introduction

 Scope
 Testing (quality control) is done at various steps
 Our focus: Only electrical tests
 Other tests: Defectivity test, etc
 Electrical Testing
 Process check (Only overall condition)
 PARAMETRIC or E-Test
 Product check (Pass/Fail for each chip)
 BIN or SORT
 RELIABILITY

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Dec 29, 2024
Review from Mask: Basics
 A mask may be 100 mm x 100 mm (for example)
 So, one ‘print’ will be about 25 mm by 25 mm, on the
wafer.
 A chip may be only 5 mm by 4 mm
 So, one mask will have perhaps 20 chips, if the chip is
small

 The gaps between the ‘real chips’


are used for
 alignment marks (TBD)
 test structures (TBD)

3
Dec 29, 2024
Process Test (parametric)
 Process Check
 Simple structures, made between the ‘real’ chips
 If the structures are very bad (all shorted, all open/ broken)
 Chips are also likely to be ‘dead’
 Not worth processing further (if the wafers are in the midst
of processing)
 Not worth testing the chips (if the wafers have completed
processing)
 So, process check is done
 in the ‘line’, at some standard steps (after M1 CMP and so on...)
 and at the end, just before the chips are tested for pass/fail
 The ‘simple structures’ used for process checks are normally called as
‘Scribe line’ or ‘Kerf’
 Process check is called “scribeline test’ or ‘kerf test’
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Dec 29, 2024
Process Test (parametric)
 Basic check for shots/opens:
 Metal lines: Snakes, Combs
 Snake & Comb for both open and
shorts
 At each layer
 Many structures
 ==> many tests, time
 few structures
 ==> lower ability to predict fails
 low resolution

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Dec 29, 2024
Process Test (parametric)
 Example of shorts:

 What is expected in
the electrical test
 Very low resistance (or high leakage current)
© micro magazine
 Plot of leakage current (CDF) CDF plot
 sorted values
 log scale to identify ppm or ppb level defects
 Stop processing the wafers with shorts/opens

 Helps isolate problematic modules 6


Dec 29, 2024
Process Test (parametric)
 VDP

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Dec 29, 2024
Tester
©Advantest
Ability to test at high temp
some may have low temp capability also

Die level vs package level

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Dec 29, 2024
Test Program
 C or script like
 Normally well commented, reasonably readable
 information on voltage applied (for example), store the data in
test name etc..
 DUT (Device Under Test)
 alignment and x,y movement

 C-V test (for oxide) OR I-V results


 time consuming
 usually one result in a DUT in a die
 TDDB, NBTI, ESD, EM

 Summary file (for water, for lot ...)


Temp. Dependent Dielectric Breakdown, Negative Bias Temperature Instability

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Dec 29, 2024
Product Test
 Binning
 Soft bin, hard bin
 initial stages, test the least failing part
 some times COF (complete on fail0
 production stage, test the most failing part
 always SOF (stop on fail)
 Continuity (leakage, open)
 Built In Self Test (BIST)
Functional
 SCAN
 Memory
 Repair (yield can improve dramatically)
 Fail Bit Map (FBM)
 WL ==> M1 short, BL fail ==> via fail (for example) (see next
slide for figure)
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Others

 High temperature test


 Optical testing

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Dec 29, 2024

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