COMPUTER

ORGANIZATION
&
ARCHITECTURE
Unit-
4
Central Processing Unit

2
 Central Processing Unit

1. Introduction
2. General Register Organization
3. Stack Organization
4. Instruction Formats
5. Addressing Modes
6. Data Transfer and Manipulation
7. Program Control
8. Reduced Instruction Set Computer(RISC)

3
Central Processing Unit

• The Components with in the CPU

1) Register Sets
2) Arithmetic and Logical Unit
3) Control Unit

• Register sets
a) Single Accumulator organization (Special purpose reg)
b) General Register Organization
c) Stack Organization
MAJOR COMPONENTS OF CPU

• Storage Components
 Registers
 Flags

• Execution (Processing) Components

 Arithmetic Logic Unit(ALU)
• Arithmetic calculations, Logical computations, Shifts/Rotates

• Transfer Components
 Bus

• Control Components
 Control Unit Register
File ALU

Control Unit
In general, most processors are organized in one of 3 ways

1. Single register (Accumulator) organization

• Basic Computer is a good example
• Accumulator is the only general purpose register

2. General register organization

• Used by most modern computer processors
• Any of the registers can be used as the source or destination for computer
operations

3. Stack organization
• All operations are done using the hardware stack
• For example, an OR instruction will pop the two top elements from the stack, do a
logical OR on them, and push the result on the stack
• In a Single Accumulator Organization there are few special purpose
registers

• In any CPU the total registers can be divided into different groups
i) General purpose registers ii) Special purpose registers

Special purpose registers General Purpose Register

1. PC – Program Counter R1
2. AR – Address Register .
3. IR – Instruction Register .
4. DR – Data Register .
5. AC – Accumulator .
6. TR – Temporary Register .
7. INRR – Input Register .
8. OUPR – Output Register .
Rn
 Control word
A general organization of seven CPU
registers
Consider R1 ← R2 + R3, the following are the
functions implemented within the CPU

• MUX A Selector (SELA) − It can place R2 into

bus A.

• MUX B Selector (SELB) − It can place R3 into

bus B.

• ALU Operation Selector (OPR) − It can select

the arithmetic addition (ADD).

• Decoder Destination Selector (SELD) − It

can transfers the result into R1.
Bus organization for CPU registers
Encoding of Register Selection Fields Encoding of ALU operations

Control word
A Stack Machine LIFO : Last In First Out

Processor A Stack machine has a stack as

a part of the processor state

stack Main typical operations:

Store push, pop, +, *, ...

: Instructions like + implicitly

specify the top 2 elements of
the stack as operands.

push b push c c pop

 b  b  b
a a a a

10
REGISTER STACK ORGANIZATION
A register stack is a memory space that uses memory words or registers
to store temporary information during program execution.
Stack
- Very useful feature for nested subroutines, nested interrupt services
- Also efficient for arithmetic expression evaluation
- Storage which can be accessed in LIFO
64 Word Stack
- Pointer: SP (stack Pointer)
- Only PUSH and POP operations are applicable
Register Stack
stack Address
Push, Pop operations 63
Flags
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */ FULL EMPTY

Stack pointer
PUSH POP 4
SP C 3
SP  SP + 1 DR  M[SP]
6 bits B 2
M[SP]  DR SP  SP  1 A 1
If (SP = 0) then (FULL  1) If (SP = 0) then (EMPTY  1) 0
EMPTY  0 FULL  0 DR
 MEMORY STACK ORGANIZATION RAM
A portion of memory is assigned to a stack operation to implement
the stack in the CPU.
1000
Program
Memory with Program, Data, and Stack Segments PC (instructions)

- A portion of memory is used as a stack with a processor register as AR

Data
a stack pointer (operands)

3000
SP
- PUSH: SP  SP - 1 - POP: DR  M[SP] stack
M[SP]  DR SP  SP + 1
3997
3998

Program Counter (PC): It is a register that points to the address of the next instruction that 3999
4000
is going to be executed in the program.
4001

Address Register (AR): This register points at the collection of data and is used during the Stack grows
In this direction
execute phase to read an operand.

Stack Pointer (SP): It points at the top of the stack and is used to push or pop the data items
in or from the stack.
• In-fix expression (X + Y)
• Pre-fix or polish notation ( +XY )
• Post fix expression or reverse polish notation (XY +)
Evaluation of Expressions

(a + b * c) / (a + d * c - e)
push a
/
push b

+ - multiply

a + e c push c
*
*
b c bb
*c
a *
a
d
c
Evaluation Stack
Reverse Polish
abc*+adc*+e-/
REVERSE POLISH NOTATION
• Arithmetic Expressions: A + B

A+B Infix notation

+AB Prefix or Polish notation
AB+ Postfix or reverse Polish notation

- The reverse Polish notation is very suitable for stack manipulation

• Evaluation of Arithmetic Expressions

Any arithmetic expression can be expressed in parenthesis-free
Polish notation, including reverse Polish notation

(3 * 4) + (5 * 6)  34*56*+

6
4 5 5 30
3 3 12 12 12 12 42
3 4 * 5 6 * +
INSTRUCTION FORMAT
• Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(es) or a processor register(s)
Mode field - determines how the address field is to be interpreted (to
get effective address or the operand)

• The number of address fields in the instruction format

depends on the internal organization of CPU

• The three most common CPU organizations:

Single accumulator organization:
ADD X /* AC  AC + M[X] */ CLA – Clear the accumulator;
CMA
General register organization:
ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */
Stack organization:
PUSH X /* TOS  M[X] */
ADD
THREE, AND TWO-ADDRESS
INSTRUCTIONS
• Three-Address Instructions

Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1  M[A] + M[B] */
ADD R2, C, D /* R2  M[C] + M[D] */
MUL X, R1, R2 /* M[X]  R1 * R2 */

- Results in short programs

- Instruction becomes long (many bits)

• Two-Address Instructions

Program to evaluate X = (A + B) * (C + D) :

MOV R1, A /* R1  M[A] */

ADD R1, B /* R1  R1 + M[A] */
MOV R2, C /* R2  M[C] */
ADD R2, D /* R2  R2 + M[D] */
MUL R1, R2 /* R1  R1 * R2 */
MOV X, R1 /* M[X]  R1 */
ONE, AND ZERO-ADDRESS INSTRUCTIONS
• One-Address Instructions
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC  M[A] */
ADD B /* AC  AC + M[B] */
STORE T /* M[T]  AC */
LOAD C /* AC  M[C] */
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
STORE X /* M[X]  AC */
• Zero-Address Instructions
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS  A */
PUSH B /* TOS  B */
ADD /* TOS  (A + B) */
PUSH C /* TOS  C */
PUSH D /* TOS  D */
ADD /* TOS  (C + D) */
MUL /* TOS  (C + D) * (A + B) */
POP X /* M[X]  TOS */
 X = (A + B) * (C + D)
Three Instruction format Two Instruction format
ADD R1, A, B R1  M[A] + M[B] MOV R1, A R1  M[A]
ADD R2, C, D R2  M[C] + M[D] ADD R1, B R1  R1 + M[B]
MOV R2, C R2  M[C]
MUL X, R1, R M[X]  R1 * R2
ADD R2, D R2  R2 + M[D]
MUL R1, R2 R1  R1 * R2
MOV X, R1 M[X]  R1

Single Instruction format

Zero Instruction format
LOAD A AC  M[A]
PUSH A TOS  A
ADD B AC  AC + M[B]
STORE T M[T]  AC PUSH B TOS  B
LOAD C AC  M[C] ADD TOS  (A + B)
ADD D AC  AC + M[D] PUSH C TOS  C
MUL T AC  AC * M[T] PUSH D TOS  D
STORE X M[X]  AC ADD TOS  (C + D)
MUL TOS  (C + D) * (A + B)
POP X M[X]  TOS
 X = (A + B) * (C + D)

Reduced instruction set Computer (RISC)

MOV R1, A R1  M[A]
MOV R2, B R2  M[B]
MOV R3, C R3  M[C]
MOV R4, A R4  M[D]
ADD R1, R2 R1  R1 + R2
ADD R3, R4 R3  R3 + R4
MUL R1, R3 R1  R1 * R3
STORE X, R1 M[X]  R1
Types of Addressing Modes

• Implied
• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Autoincrement or AutoDecrement
• Relative
• Indexed
• Base Register
An assembly language program instruction consists of two parts
Implied Addressing Mode
• Implied Mode
Address of the operands are specified implicitly in the definition of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP]
- Examples from Basic Computer
CLA, CME, INP

Zero address instruction are designed with implied

addressing mode.
Immediate Addressing
• Immediate Mode
Instead of specifying the address of the operand,
operand itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand

Instruction
• e.g. ADD 5
• Add 5 to contents of accumulator Opcode Operand
• 5 is operand

Example: MOV AL, 35H (move the data 35H into AL register)
Direct Addressing

• Direct Address Mode

Instruction specifies the memory address which can be used
directly to access the memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address
for a large physical memory space
- EA = IR(addr) (IR(addr): address field of IR)

• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
 Direct Addressing Diagram

Instruction
Opcode Address A
Memory

Operand

Example: ADD AL,[0301] //add the contents of offset address 0301 to AL

Indirect Addressing
• Indirect Addressing Mode
The address field of an instruction specifies the address of a
memory location that contains the address of the operand
- When the abbreviated address is used large physical memory can
be addressed with a relatively small number of bits
- Slow to acquire an operand because of an additional memory
access
- EA = M[IR(address)]

• EA = (A)
– Look in A, find address (A) and look there for operand
• e.g. ADD (A)
– Add contents of cell pointed to by contents of A to accumulator
Indirect Addressing Diagram

Instruction
Opcode Address A
Memory

Pointer to operand

Operand
Register Addressing

• Register Mode
Address specified in the instruction is the register address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory
addressing
- EA = IR(R) (IR(R): Register field of IR)
• EA = R
Register Addressing Diagram

Instruction
Opcode Register Address R Registers

Operand
 Register Indirect Addressing

• Register Indirect Mode

Instruction specifies a register which contains the memory
address of the operand
- Saving instruction bits since register address
is shorter than the memory address
- Slower to acquire an operand than both the
register addressing or memory addressing
- EA = [IR(R)] ([x]: Content of x)

• EA = (R)
Register Indirect Addressing Diagram

Instruction
Opcode Register Address R
Memory

Registers

Pointer to Operand Operand

Index Addressing Diagram

Instruction
Opcode Register R Address A
Memory

Registers

Pointer to Operand + Operand

 DATA TRANSFER INSTRUCTIONS
Name Mnemonic
• Typical Data Transfer Instructions Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

• Data Transfer Instructions with Different Addressing Modes

Assembly
Mode Convention Register Transfer
Direct address LD ADR AC M[ADR]
Indirect address LD @ADR AC  M[M[ADR]]
Relative address LD $ADR AC  M[PC + ADR]
Immediate operand LD #NBR AC  NBR
Index addressing LD ADR(X) AC  M[ADR + XR]
Register LD R1 AC  R1
Register indirect LD (R1) AC  M[R1]
Autoincrement LD (R1)+ AC  M[R1], R1  R1 + 1
Autodecrement LD -(R1) R1  R1 - 1, AC  M[R1]
DATA MANIPULATION INSTRUCTIONS
• Three Basic Types: Arithmetic instructions
Logical and bit manipulation instructions
Shift instructions
• Arithmetic Instructions
Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with Carry ADDC
Subtract with Borrow SUBB
Negate(2’s Complement) NEG

• Logical and Bit Manipulation Instructions

Name Mnemonic • Shift Instructions
Clear CLR Name Mnemonic
Complement COM Logical shift right SHR
AND AND Logical shift left SHL
OR OR Arithmetic shift right SHRA
Exclusive-OR XOR Arithmetic shift left SHLA
Clear carry CLRC Rotate right ROR
Set carry SETC Rotate left ROL
Complement carry COMC Rotate right thru carry RORC
Enable interrupt EI Rotate left thru carry ROLC
Disable interrupt DI
Control memory
Address Sequencing
Micro Programme Example
Design of Control Unit