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5 VerificationPlan

The document outlines a Verification Plan, detailing its purpose, methodologies, and approaches such as Black-Box, White Box, and Grey Box verification. It discusses various testing methodologies, including Directed Testing and Constrained Random Testing, highlighting their advantages and disadvantages. Additionally, it covers the importance of Functional and Code Coverage in ensuring all essential features are verified effectively.

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0 views16 pages

5 VerificationPlan

The document outlines a Verification Plan, detailing its purpose, methodologies, and approaches such as Black-Box, White Box, and Grey Box verification. It discusses various testing methodologies, including Directed Testing and Constrained Random Testing, highlighting their advantages and disadvantages. Additionally, it covers the importance of Functional and Code Coverage in ensuring all essential features are verified effectively.

Uploaded by

starlordhero1607
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Verification Plan and

Methodologies
What is a Verification Plan?
• Specification document for verification effort
– Mechanism to ensure all essential features are
verified as needed
• What to verify ?
– Features and under what conditions to verify them
• How to verify ?
– What methodologies to use – Formal, Checking,
Coverage etc.
– What should be - Stimulus, Checkers, Coverage
• Priority for features to be verified

07/16/2025 Verification with System Verilog 2


Verification Approaches
• Black-Box
 Verification without knowledge of design implementation.
 Lack of visibility and observability.
 Tests are independent of implementation.
 Impractical in todays designs.
• White Box
 Intimate knowledge of design implementation
 Full visibility and observability
 Tests are tied to a specific implementation
• Grey Box
 Compromise between above approaches

07/16/2025 Verification with System Verilog 3


Levels of Verification

• Each level of Verification will


be suited for a specific
objective
– Lower levels have better
controllability and visibility
• Block level Verification helps
designs to be verified
independently and in parallel
• System Level Verification
focuses more on interactions

07/16/2025 Verification with System Verilog 4


Verification Process

Read section 1.2


Features of verification language (System
Verilog)
Basic Test bench Functionality
Types of Testing Methodologies

• Directed Testing

• Constrained Random testing


Directed Test

• Using specifications, write verification plan with list of tests, focusing on each
feature
• Apply corresponding stimulus and verify log files and waveforms manually
• Incremental procedure, where tests are covered one by one
• Produces immediate results, since we check creation of every stimulus vector.

Advantage: covers all test, 100% coverage


Disadvantages :
Time consuming/ excessive man power and resources required
Rate of progress (slope) remains same. Hence if complexity doubles, time
required doubles)
Constrained Random Testing
• We don’t use completely random stimulus
• Some kind of constraints if put eg: 32 bit address, length of data, precision of
input)

• Simulator uses those random values that meet these constraints


• These are given to design and output noted down.
• The same inputs are given to a top level model which predicts the expected
output.
• The actual output is compared with the predicted output
Constrained Random Testing

• In this random stimulus is applied (automatic generation of stimulus, crucial for


complex designs.)
• Directed tests finds bugs that you had expected while random tests find unexpected
bugs.
• Since stimulus is random, we need automatic way to predict results and identify
correctness [reference model/score board]
• Build a test infrastructure that will be shared by all tests.
• In the test-structure, leave spaces and hooks where stimulus generation can be done.
• Important: we don’t write code that is specific to a single test. It is a general structure
which is modified for different tests.
Constrained Random Testing
Advantages: Each test shares this common test bench (with a few lines of code added for
stimulus and checking for exceptions), while in directed testing each test is written from
scratch.
Find bugs faster.

Disadvantages :
Requires lot of time in the beginning to set up the test structure
Most of bugs found but some bugs have to be found only by directed testing..

Initial delay but faster


overall
Coverage
Functional Coverage:
Create a test plan that tracks whether important values, sets of values, or sequences
of values that correspond to design or interface requirements, features, or boundary
conditions have been exercised.

100% functional coverage indicates that all items in the test plan have been tested.

Note: Functional coverage is user specified. We provide input file that specifies what
all needs to be covered.

Code Coverage:
Code coverage tracks what lines of code or expressions in the code have been
exercised.

100% code coverage implies that all expressions in code have been executed.

Code coverage is done automatically by the tool. There is no input from the user.
Functional Coverage
Functional Coverage convergence
Start from here

Spend most of time in outer loop.. Only when coverage doesn’t


improve, then write directed tests to for those test that can’t
be reached by random tests.
• Self Study
sections 1.9, 1.10

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