Papers by Michael Cracraft
ABSTRACT The connection of the logic ground to the chassis can influence a number of EMC factors ... more ABSTRACT The connection of the logic ground to the chassis can influence a number of EMC factors such as emissions, RF immunity, and ESD immunity. Improper connections can turn the chassis into an unintended radiator. Historically, two different grounding strategies have been used. Printed circuit boards are either connected in many locations through low impedance paths, or a single point connection is used with any other connections using high-impedances. Both have been applied successfully in the past, but mixing the two could have unintended consequences. In order to adapt to such environments a designer may desire some flexibility, such as the ability to open or short a particular ground connection without major PCB changes. This paper discusses utilizing components such as 0-ohm resistors in place of direct short connections between logic ground and the chassis. The additional parasitic inductance incurred is quantified relative to direct connections for a number of configurations.
IBM Journal of Research and Development, 2015
IBM z13 processor drawer W. D. Becker H. Harrer A. Huber W. L. Brodsky R. Krabbenhoft M. A. Cracr... more IBM z13 processor drawer W. D. Becker H. Harrer A. Huber W. L. Brodsky R. Krabbenhoft M. A. Cracraft D. Kaller G. Edlund T. Strach The electronic packaging of the IBM z13i is the foundation for a processor drawer that provides a significant increase in processing power relative to the IBM zEnterpriseA EC12 (zEC12) system while managing power and cost to meet the z13 product objectives. The z13 system architecture differs from previous high-end z Systemsi designs due to the introduction of a drawer-based processor design, organic single-chip modules (SCMs) in place of the ceramic MCMs (multi-chip modules), and a cabled interconnect between drawers in place of the PCB (printed circuit board) backplane of the zEC12. These innovations are coupled with next-generation signaling interfaces, providing a significant increase in signal bandwidth. The next-generation voltage regulation and decoupling provides the efficient power delivery needed to build a new processor subsystem with 40% more processor cores than the zEC12. The memory bandwidth and capacity have more than tripled, and the input/output bandwidth of the processor chip doubled to provide excellent scalability at the processor socket, drawer, and system level. The electronic packaging has been designed to meet all of these challenges, and this paper presents the design and integration of the electronic packaging of the z13 system.
2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), 2017
Common mode (CM) conversion in differential communication links represents serious signal integri... more Common mode (CM) conversion in differential communication links represents serious signal integrity (SI) and electromagnetic compatibility (EMC) hazards. Two types of common-mode filtering structures are investigated in this paper. The first employs complementary split ring resonator (CSRR) structures placed in the reference layer surrounded by via fences, and the second uses a composite right-/left-handed (CRLH) structure formed by placing metallic strips between the microstrip traces. Via fences were employed to surround the individual CSRR filtering structures, which allows cascading to either filter at multiple frequencies or else to broaden filtering bands. Via fences also prevent filtered CM energy from exciting parallel-plane waveguide (PPW) modes which would degrade the board's EMC and SI environments.
2018 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (EMC, SI & PI), 2018
A physics-based circuit modeling methodology is proposed in this paper for system level power int... more A physics-based circuit modeling methodology is proposed in this paper for system level power integrity (PI) analysis. The circuit model is extracted by following the current paths in the system PDN based on cavity model and plane-pair PEEC models. The modeling methodology connects the footprints of geometry details to the PDN input impedance looking into the system from the IC chip. With further reductions of the physics-based circuit model, an engineering circuit model which explains the hierarchical charge delivery mechanism is proposed. The engineering circuit model reveals the role of PDNs from each level in the system. A commercial PDN system with a complex organic package, high-layer-count printed circuit board, and IC is used to validate the modeling methodology in the paper. The PDN input impedance has a good match with the impedance profile simulated with a commercial PI analysis tool for the system. The engineering circuit model is also validated for the PI analysis. The modeling methodology illustrates the fundamental physics in the PDN charge delivery and can be used for other PI analysis later.
2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020
This paper presents a cost-effective method using 3D printing technology to reduce the parasitic ... more This paper presents a cost-effective method using 3D printing technology to reduce the parasitic losses when probing a channel with a logic analyzer compared to traditional methods. The method is demonstrated on a 16 Gb/s PCIe Gen4 channel, taking advantage of the physically accessible SMT AC decoupling capacitors through a custom fixture to contact the signals of the high-speed serial (HSS) channel.Channel topology, length and transceiver compensation, and sophisticated equalization has increased link frequency dramatically at the cost of complexity. This renders traditional debug activities using an oscilloscope to be of very limited value in the characterization and verification of the link. The protocol-awareness of HSS links, including the use of retimers, makes the use of a logic analyzer necessary.While a logic analyzer fills the need for protocol analysis and timing data to debug link errors that would be undetected by traditional oscilloscope efforts, the fixturing to conta...
IEEE Transactions on Electromagnetic Compatibility, 2015
This paper deals with the filters based on EBG cavities employed for reducing common-mode current... more This paper deals with the filters based on EBG cavities employed for reducing common-mode currents along differential stripline traces. The crosstalk among differential interconnects routed in close proximity to EBG-based filters, and next to filtered pairs, is accurately quantified. The comparison between the experimental and simulation frequency-domain results validate the proposed filter's effectiveness and make the simulation model reliable for investigating the complex multichannel crosstalk problem. This paper focuses on the stripline environment, where crosstalk occurs among traces routed on adjacent layers, with the EBG cavity acting as a coupling path. Multichannel time-domain simulations complete the characterization of the filter, showing the limited effects of the filter on the intentional differential signal, and the beneficial impact on reducing the potentially radiating commonmode harmonics. The quantification of the common-mode spectrum shows that the filtered harmonics are reduced by 10-15 dB; thus, minimizing the corresponding electromagnetic interference. Design guidelines are defined for the filter layout according to the relative position of unfiltered differential traces, when constraints force them to be placed in close proximity to EBG cavities and filtered pairs. In particular, the best layout for unfiltered traces on adjacent layers is orthogonal with respect to the filtered pair, whereas the parallel routing should be carefully used taking into account the signal bandwidth on the victim pairs.
2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC), 2016
A transient simulation analysis is proposed for printed circuit board (PCB) power distribution ne... more A transient simulation analysis is proposed for printed circuit board (PCB) power distribution network (PDN) by using physics based circuit model. The PCB PDN is divided into different blocks. Different modeling methods are used to provide physics-based circuit models for each block. Then, Hspice simulation is used to do transient simulation for the PCB PDN based on the circuit.
2021 IEEE International Joint EMC/SI/PI and EMC Europe Symposium
Progress In Electromagnetics Research C
Differential signaling is used in digital circuitry and high speed communication links due to its... more Differential signaling is used in digital circuitry and high speed communication links due to its lower level of radiation and lower susceptibility to interference. Signal skew, amplitude differences and unequal parasitic electric or magnetic coupling to nearby structures can lead to common-mode signals being present on differential communication links which can result in unwanted electromagnetic interference and crosstalk. Common-mode filtering is often employed to suppress common-mode signal propagation in order to mitigate against these negative effects. In this paper broadside coupled differential coplanar waveguides are used which provide effective differential transmission from dc through 40 GHz. Simulation and measurement show that dipole-like common-mode filtering elements placed between the broadside coupled traces offer common-mode suppression of more than 10 dB over bandwidths greater than 5 GHz. A design equation is developed which can be used to estimate filtering frequencies from filter dimensions through 30 GHz. Filters can be cascaded to broaden filtering around a single frequency to filter at multiple frequencies. Simulation based registration studies were conducted which show stable filtering performance in the presence of layer-to-layer misregistration up to 0.254 mm.
2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity, 2015
2014 IEEE International Symposium on Electromagnetic Compatibility (EMC), 2014
2013 IEEE International Symposium on Electromagnetic Compatibility, 2013
ABSTRACT The connection of the logic ground to the chassis can influence a number of EMC factors ... more ABSTRACT The connection of the logic ground to the chassis can influence a number of EMC factors such as emissions, RF immunity, and ESD immunity. Improper connections can turn the chassis into an unintended radiator. Historically, two different grounding strategies have been used. Printed circuit boards are either connected in many locations through low impedance paths, or a single point connection is used with any other connections using high-impedances. Both have been applied successfully in the past, but mixing the two could have unintended consequences. In order to adapt to such environments a designer may desire some flexibility, such as the ability to open or short a particular ground connection without major PCB changes. This paper discusses utilizing components such as 0-ohm resistors in place of direct short connections between logic ground and the chassis. The additional parasitic inductance incurred is quantified relative to direct connections for a number of configurations.
2013 IEEE International Symposium on Electromagnetic Compatibility, 2013
ABSTRACT Differential wiring is prevalent in high-speed signaling, because it provides better imm... more ABSTRACT Differential wiring is prevalent in high-speed signaling, because it provides better immunity and reduced emissions over single-ended transmission structures. These advantages are diminished when the transmitter pollutes the signal with common mode signals and when discontinuities in the channel convert some fraction of the differential mode signal to common mode. This paper focuses on the channel discontinuities, specifically the arrangement of signal and return vias. Genetic algorithms and a fast via solver are used to optimize return positions to minimize the mode conversion. Case studies of open-area via transitions are presented, as well as a pin array conforming to a common high-speed connector footprint.
2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), 2016
2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), 2016
2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), 2016
IEEE Transactions on Electromagnetic Compatibility, 2016
2016 IEEE/ACES International Conference on Wireless Information Technology and Systems (ICWITS) and Applied Computational Electromagnetics (ACES), 2016
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Papers by Michael Cracraft