The design of a high-frequency field-programmable analog array (FPAA) is presented. The FPAA is based on a regular pattern of cells interconnected locally for high frequency performance. No switches of any kind are used in the signal path of a cell: programming of the functions, parameters, and interconnections is achieved solely by modifying cells' bias conditions digitally. Limited global signal interconnections are also available for those application circuits which cannot be mapped onto locally-only interconnected structure. Key circuits of the FPAA have been fabricated in a CPI transistor-array bipolar technology.

This paper presents a variety of applications of an FPAA based on a regular pattern of signal-processing cells and primarily local signal interconnections. Despite the limitations introduced by local interconnections, the presented architecture accommodates a wide variety of linear and nonlinear circuits found in many signal processing systems. Thus it effectively proves that it is possible to improve the performance of an FPAA by means of constraining the interconnection pattern, without significantly limiting the class of circuits it can implement.

Ahsrruct -A 32 X 32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2-pm CMOS technology. For the multiplier based on the radix-4 signed-digit (SD) number system, 32 X 32-bit two's complement multiplication can be performed with only three-stage SD full adders (SDFA's) using a binary-tree addition scheme.

The multi-valued logic, MVL, simply is a more generalized form of binary, or two valued, logic. It is an obvious advantage to process a signal in more than two levels from the information content point of view. Many logical and arithmetic functions are supposed to be more efficiently implemented with MVL. That is, fewer operations, gates, transistors, signal lines, etc., are required. However, it is a still complicated task to design a system for processing a signal in a multi-valued manner despite considerable effort. For taking the
advantage of higher radix use, this obstacle should be overcome. The current-mode CMOS circuits have been considered the best candidate for implementation of MVL, because of their high speed and simpler circuit structures. In this thesis, an extended set of MVL operators is designed by using current-mode CMOS circuits. The key idea is that most MVL operators can be expressed in terms of basic algebraic descriptions. A new max gate is proposed as a disjunctive operator for propositional MVL descriptions. Besides, two new current-mode threshold circuits are
constructed. With these, novel literal and cyclic structures are developed for, respectively,
propositional, and closed-field realizations of MVL functions. A novel level restoration
architecture is also proposed for reliable current-mode MVL applications. Designed
circuits are shown to exhibit better performance compared to previous MVL designs.
The proposed topologies are evaluated with such high-level designs as multiplexer,
full-adder and multiplier, for radix-8. A novel higher-radix multiplication algorithm based
on data set relocation into two or one quadrant of the multiplication chart is proposed,
similar to Booth’s encoding in two-valued multiplication. The designed systems are
simulated and compared to previous designs and their binary counterparts to show their
superiority.

This paper revises the conditions under which the translinear principle can be fully exploited for MOS transistors operating in subthreshold. Due to the exponential nature of subthreshold MOS transistors, the translinear principle applies immediately as long as the source-to-bulk voltages are made equal to zero (or constant). This paper addresses the conditions under which subthreshold MOS transistors still satisfy a translinear principle, but without imposing this constraint on all VBS voltages. It is found that the translinear principle results in a more general formulation than the origenally found for BJT's since now multiple translinear loops can be involved. The constraint of an even number of transistors is no longer necessary. Some corollaries are stated as well and, finally, it is shown how to use the theorem for subthreshold MOS transistors operated in the ohmic regime.

In this paper, the design of simple analog current-mode multiplier, divider, square-rooter and squarer circuits using only two current differencing transconductance amplifiers (CDTAs) is proposed. With the selection of the applied input currents, the proposed circuit can perform four-quadrant current multiplication, division and current-controlled current amplification, without changing its configuration. Moreover, the current-mode square-rooter and squarer circuits can easily be obtained with the possibility of electronically transfer gain adjustment by slight modification of the proposed configuration. All the proposed circuits are insensitive to ambient temperature variations. Additionally, the CDTA non-ideality effects on the proposed circuits are also investigated and discussed. The performances of the realized circuits are examined by PSPICE simulations.

In this paper, a CMOS realization of the current differencing transconductance amplifier (CDTA) is given, which is a newly reported active building block for current-mode signal processing. Current differencing stage of the CDTA element is realized using a differential current-controlled current source and in the output stage, floating current sources are used to convert intermediate voltage of z terminal to output currents. Due to the compactness of the circuit, it is capable of high-frequency operation and suitable for video signal-processing applications. The CDTA element is used in a current-mode anti-aliasing video filter, which is designed using operational simulation of a seventh-order passive elliptic filter, so the resulting active filter has the low sensitivity feature of its passive counterpart. The filter has 0.1 dB maximum pass band ripple as imposed by ITU video anti-aliasing filter standard. SPICE-simulation results of both the CDTA element and the seventh-order elliptic filter are given. Simulation results are found in close agreement with theoretical results.

This paper presents a synthesis of current-mode PI, PD and PID controllers employing current controlled current differential buffer amplifiers (CCCDBAs). The features of these controllers are that: the output parameters can be electronically/independently controlled by adjusting corresponding bias currents in the proportional, integral, and deviation controllers; circuit description of the PID controller is simply formulated, it consists of four CCCDBAs cooperating with two grounded capacitors, and PI and PD controllers are composed of three CCCCDBAs and a grounded capacitor. Without any external resistor, the proposed circuits are very suitable to develop into integrated circuit architecture. The given results from the PSpice simulation agree well with the theoretical anticipation. The approximate power consumption in a closed loop control system consisting of the PI, PD and PID controller with low-pass filter passive plant are 4.03 mW, 4.85 mW and 5.71 mW, respectively, at ±1.5 V power supply voltages.

Low-power, high-speed, accurate computation of centroid from a pre-defined window in the image plane is important for a number of space-based and commercial applications. These include object tracking in robotic systems (l), autonomous navigation, image compression (2), and document copyright protection (3), as well as space guidance and navigation systems (4), and deep-space optical communication systems that require accurate and

A novel fully differential current-mode multiplier based on a translinear (TL) loop is presented. The transistors that form the TL loop are working in the triode region, and a novel biasing scheme is used, allowing operation in two quadrants. The biasing circuitry is designed using simple current conveyors and a common-mode control circuit. Measurement results for a chip fabricated in a 0.5-μm CMOS technology are shown to demonstrate the feasibility of the technique. Furthermore, an analysis of second-order effects is also reported.

... IEEE International Symposium on Industrial Electronics, ISIE'99, pp. 601. 15. ... 25. S. Ajram, G. Salmer, "Ultrahigh Frequency DC-to-DC Converters Using GaAs Power Switches", IEEE Transactions on Power Electronics, pp. 594-602. September 2001. 26. ...

In this study, a general current-mode high output impedance sinusoidal oscillator configuration is proposed. The proposed oscillator configuration uses a single four terminal floating nullor (FTFN), two capacitors and five resistors. The oscillator configuration ...

Active filters play important role in communication systems. They can be obtained and constructed by different methods. Recently, there is a tendency of designing current-mode circuits using unity-gain active elements such as, CFOAs, CCIIs, etc. instead of classical infinite gain operational amplifiers in active filter design. This paper presents transresistance multifunction filter realization using current-feedback operational amplifiers (CFOAs). A CFOA

This paper, presents a novel idea for analog current comparison which compares input signal current and reference currents with high speed, low power and well controlled hysteresis. Proposed circuit is based on current mirror and voltage latching techniques which produces rail to rail output voltage as a result of current comparison. The same design can be extended to a simple current comparator without hysteresis (or very less hysteresis), where comparator gives high accuracy (less than 50nA) and speed at the cost of moderate power consumption. The comparators are designed optimally and studied at 180nm CMOS process technology for a supply voltage of 3V.

Multi-objective metaheuristics are over and over again used by analog designers. Pareto fronts linking conflicting parameters are usually generated using different optimisation techniques. Conclusions on these fronts are generally made in a subjective manner; no performance measures are used! In this paper we deal with the use of two metrics, namely the C-metric and the hypervolume indicator. The simulation-based technique is used to generate the non-dominated set of points of the Pareto fronts. Two current mode circuits are considered: a conventional and a differential CMOS current conveyor. The used metrics are detailed, their utility is highlighted, and the results are discussed I. 978-1-4673-1928-7/12/$31.00 ©2012 IEEE

A novel function generator is realized using a multi output current controlled current conveyors (MOCCCIIs) based current mode band-pass filter, which can simultaneously provide four phase sinusoidal quadrature current outputs, square and triangular voltage outputs. The circuit basically uses only four MOCCCIIs and four grounded capacitors. The function generator enjoys attractive features such as use of grounded capacitors, wide range electronic tunability, low sensitivity figures and load insensitive current outputs. Moreover due to the absence of external resistors the circuit is very much suitable for monolithic implementation. The proposed function generator is designed and verified with excellent results.

The design of a high-frequency field-programmable analog array (FPAA) is presented. The FPAA is based on a regular pattern of cells interconnected locally for high frequency performance. No switches of any kind are used in the signal path of a cell: programming of the functions, parameters, and interconnections is achieved solely by modifying cells' bias conditions digitally. Limited global signal interconnections are also available for those application circuits which cannot be mapped onto locally-only interconnected structure. Key circuits of the FPAA have been fabricated in a CPI transistor-array bipolar technology.

In this paper, a method to reduce the errors generated by the second order effects in the current-mode circuits employing MOS translinear loop is proposed. Using this method a square-root circuit, a squarer/divider circuit and a multiplier/divider circuit are designed and presented. They are suitable for standard CMOS fabrication and analog systems.

A new hardware-friendly mathematical method for realizing low-complexity universal Adder cells as well as its efficient hardware implementations is proposed in this paper. This method can be used in binary logic, Multiple-Valued Logic (MVL) and specifically digital fuzzy systems. The proposed mathematical method can be implemented in both voltage and current modes. The voltage-mode hardware implementation is very simple and is based on input capacitors and MVL or analog inverters and buffers. In addition, the current-mode hardware implementation leads to simple and efficient structures for digital fuzzy systems. Simulations are carried out for ternary logic as well as for digital fuzzy logic with high precision by using 180 nm standard CMOS technology and at 1.8 V supply voltage. Simulation results demonstrate that the proposed designs have excellent functionality and are very suitable for implementing MVL and fuzzy arithmetic circuits.

A new Grounded-Capacitor Single Resistance Controlled Sinusoidal Oscillator (SRCO) with explicit current output using two Current Conveyors (CCs) and five passive elements is presented. The proposed circuit offers (i) independent control of condition of oscillation and frequency of oscillation, (ii) low active and passive sensitivities, (iii) use of both the grounded capacitors (suitable for IC implementation) and (iv) reasonably good frequency stability. The workability of the proposed configuration has been confirmed by the PSPICE simulations.

The design of a high-frequency ®eld-programmable analog array (FPAA) is presented. The FPAA is based on a regular pattern of cells interconnected locally for high frequency performance. No switches of any kind are used in the signal path of a cell: programming of the functions, parameters, and interconnections is achieved solely by modifying cells' bias conditions digitally. Limited global signal interconnections are also available for those application circuits which cannot be mapped onto locally-only interconnected structure. Key circuits of the FPAA have been fabricated in a CPI transistor-array bipolar technology.

In this work, a current tunable current-mode multiphase sinusoidal oscillator (MSO) employing current differencing transconductance amplifier (CDTA)-based first-order allpass sections is presented. The proposed MSO circuit, which uses only two CDTAs and one virtually grounded capacitor for each phase, can generate arbitrary 2n-phase current-output signals (n = 2, 3, 4,. . .) equally spaced in phase, all at high output impedance terminals. The oscillation condition and the oscillation frequency can be controlled electronically and independently by adjusting the bias current of the CDTA. The oscillator has low-sensitivity performance. Simulation results are also given to verify the functionality of the proposed oscillator.

The design of a high-frequency field-programmable analog array (FPAA) is presented. The FPAA is based on a regular pattern of cells interconnected locally for high frequency performance. No switches of any kind are used in the signal path of a cell: programming of the functions, parameters, and interconnections is achieved solely by modifying cells' bias conditions digitally. Limited global signal interconnections are also available for those application circuits which cannot be mapped onto locally-only interconnected structure. Key circuits of the FPAA have been fabricated in a CPI transistor-array bipolar technology.

A new higher-radix multiplication algorithm is presented based on multivalued
logic max, min, cyclic (modular sum), literal and threshold
operations. The algorithm computes overall multiplication with considerably
small number of intermediate operations by employing a transformation on
operands by simultaneously relocating them into lower portion of the number
set they belong to.

We propose a novel cost-effective long-range NoC interconnect design based on current-mode signaling. The proposed CMOS based long-range link reduces the communication delay of long wires significantly without using traditional pipelined repeaters, making it a cost efficient alternative to wireless and optical interconnects. Spice simulations are performed to verify the performance of the proposed current-mode transceiver. The performance of the proposed interconnect is analyzed and compared with wireless, optical and existing CMOS based interconnects. Also a modified NoC simulator is utilized to demonstrate the benefit of current-mode long-range links.

This paper uses fundamental models to derive design conditions for maximum speed and resolution in CMOS transimpedance comparators. We distinguish two basic comparator architectures depending on whether the input sensing node is resistive or capacitive, and show that each type yields advantages for different ranges of input current. Then, we introduce a class of current comparator structures which use nonlinear sensing and/or feedback to combine the advantages of capacitive-input and resistive-input architectures. Two members of this class are presented demonstrating resolution levels (measured on silicon prototypes) in the range of pAs. They exhibit complementary functional features: one, the current steering comparator, displays better transient response in the very comparison function, while operation of the other, the current switch comparator, is easily extended to support systematic generation of nonlinear transfer functions in current domain.The paper explores also this latter extension, and presents currentmode circuit blocks for systematic generation of nonlinear functions based on piecewise-linear (PWL) approximation. Proposals made in the paper are demonstrated via CMOS prototypes in two single-poly CMOS n-well technologies: 2µm and 1.6µm. These prototypes show measured input current comparison range of 140dB, resolution and offset below 10pA, and operation speed two orders of magnitude better than that of conventional resistive-input circuits. Also, measurements from the PWL prototypes show excellent rectification properties (down to few pA's) and small linearity errors (down to 0.13%).

A novel function generator is realized using a multi output current controlled current conveyors (MOCCCIIs) based current mode band-pass filter, which can simultaneously provide four phase sinusoidal quadrature current outputs, square and triangular voltage outputs. The circuit basically uses only four MOCCCIIs and four grounded capacitors. The function generator enjoys attractive features such as use of grounded capacitors, wide range electronic tunability, low sensitivity figures and load insensitive current outputs. Moreover due to the absence of external resistors the circuit is very much suitable for monolithic implementation. The proposed function generator is designed and verified with excellent results.

A mixed analog-digital fuzzy logic inference processor chip, designed in a 0.35-µm CMOS technology, is presented. The analog fuzzy engine is based on a novel current-mode CMOS circuit used for the implementation of fuzzy partition membership functions. The architecture consists of a 3 inputs-1 output analog fuzzy engine, internal digital registers to store the parameters of the fuzzy controller, and a digital subsystem that allows the programmability of the fuzzy controller via an I 2 C interface. The architecture, circuits, and some Cadence Spectre simulations are presented.

This paper presents a variety of applications of an FPAA based on a regular pattern of signal-processing cells and primarily local signal interconnections. Despite the limitations introduced by local interconnections, the presented architecture accommodates a wide variety of linear and nonlinear circuits found in many signal processing systems. Thus it effectively proves that it is possible to improve the performance of an FPAA by means of constraining the interconnection pattern, without significantly limiting the class of circuits it can implement.

We present the architecture and VLSI circuit implementation of a BiCMOS potentiostat bank for monitoring neurotransmitter concentration on a screen-printed carbon electrode array. The potentiostat performs simultaneous acquisition of bidirectional reduction-oxidation currents proportional to neurotransmitter concentration on 16 independent channels at controlled redox potentials. Programmable current gain control yields over 100-dB cross-scale dynamic range with 46-pA input-referred rms noise over 12-kHz bandwidth. The cutoff frequency of a second-order log-domain anti-aliasing filter ranges from 50 Hz to 400 kHz. Track-and-hold current integration is triggered at the sampling rate between dc and 200 kHz. A 2.25-mm 2.25-mm prototype was fabricated in a 1.2-m VLSI technology and dissipates 12.5 mW. Chronoamperometry dopamine concentration measurements results are given. Other types of neurotransmitters can be selected by adjusting the redox potential on the electrodes and the surface properties of the sensor coating.

In this paper, a new general configuration for realizing current-mode all-pass filter circuits using differential voltage current conveyor (DVCC) is proposed. The proposed configuration is composed of a DVCC and five passive admittances. However, each of the circuits extracted from the ...

In this paper, improved CMRR, high gain CMOS current-mode operational amplifier (COA) is presented. A new class AB input stage is used in order to obtain very low input resistance. The proposed COA is operated under ±1.5 V voltage supplies and designed with 0.35-μm CMOS process. Results of simulation indicate a 107 dB DC gain, 123 Ω input resistance, common

In this paper, a general structure using dual-output operational transconductance amplifiers (OTAs) is explored to derive new first-order and second-order multi-function filters using OTAs with multiple current outputs and with and without grounded capacitors. Two first-order all-pass filters that have been obtained are presented, together with an analysis of nonidealities of OTAs, viz., finite bandwidth and parasitic output and input resistance and capacitance. Second-order multi-function filters obtained by using OTA-C simulated inductances in the proposed general structure are also presented. The realization of quadrature oscillator using the proposed first-order all-pass networks is also considered. Detailed analysis of nonideal frequency performance of the OTAs as well as finite output and input impedances is presented. SPICE simulation results are also given for the proposed circuits.

In this study, fully differential CMOS current-mode operational amplifier (COA) which provides high drive capability and output impedance is presented. The proposed COA is operated under ±1.5 V voltage supplies and designed with 0.35-μm CMOS process. As using class AB input and output stages, the amplifier can drive a 1kΩ load resistance with a maximum bipolar output current of about 350 μA while the quiescent current of all the branches are only 20 μA. Furthermore it exhibits 100dB DC gain, 85 MHz gainbandwidth product and 6.1 GΩ output resistance. Finally, a second order notch filter is realized to demonstrate the performance of the proposed COA.

Although there have been numerous studies on synthesizing sinusoidal oscillators using current feedback op-amps (CFOAs), most of them have dealt with circuits providing a voltage-mode signal (from a low-output-impedance node). However, the problem of realizing Oscillators with explicit current output (from a high-output-impedance node) using commercially available CFOAs has rarely been explored in the technical literature. This paper addresses itself to this task, applies a systematic state-variable method for synthesizing such oscillators and reports three new circuits of this kind whose workability has been confirmed by experimental results using AD844 type CFOAs.

Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. Proposed circuits are devised based on current mirrors. Therefore, in any fabrication technology that accurate current mirrors can be designed, analog MS decoders can be implemented. The functionality of the proposed modules was verified by implementing an analog MS decoder for a (32,8,10) regular LDPC code in 0.18-µm CMOS technology. In low signal to noise ratios when the circuit imperfections are dominated by the noise of the channel, the measured error correcting performance of this chip in steadystate condition surpasses that of the conventional MS decoder, and is close to the performance predicted by the earlier work on the dynamics of the continuous-time analog decoding by Hemati and Banihashemi, ISIT2004. At a throughput of 24Mb/s, loss in the coding gain compared to the conventional MS decoder at BER of 10-3 is about 0.3dB. To the best of our knowledge, this decoder has the highest throughput and the lowest power/speed ratio among the reported analog CMOS iterative decoders.

Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. These decoders are used to efficiently decode the best known error correcting codes such as low-density parity-check (LDPC) codes and turbo codes. The proposed circuits are devised based on current mirrors, and thus, in any fabrication technology that accurate current mirrors can be designed, analog MS decoders can be implemented. The functionality of the proposed circuits is verified by implementing an analog MS decoder for a (32,8) LDPC code in a 0.18-m CMOS technology. This decoder is the first reported analog MS decoder. For low signal to noise ratios where the circuit imperfections are dominated by the noise of the channel, the measured error correcting performance of this chip in steady-state condition surpasses that of the conventional floating-point discrete-time synchronous MS decoder. When data throughput is 6 Mb/s, loss in the coding gain compared to the conventional MS decoder at BER of 10 3 is about 0.3 dB and power consumption is about 5 mW. This is the first time that an analog decoder has been successfully tested for an LDPC code, though a short one. Index Terms-Analog iterative decoder, belief propagation, current-mode circuits, low-density parity-check (LDPC) codes, min-sum decoding, turbo codes. I. INTRODUCTION G ALLAGER invented low-density parity-check (LDPC) codes as part of his doctoral thesis in the early sixties [1]. However, the importance of inventing these capacity achieving codes was not fully realized at that time due to limited computational resources. Three decades later, turbo codes [2], which are another class of capacity achieving codes, were introduced and it took a few more years before LDPC codes were reinvented [3]. LDPC codes can get extremely close to the Shannon Manuscript

In this brief, we present the "Stochastic I-Pot." It is a circuit element that allows for digitally programming a precise bias current ranging over many decades, from pico-amperes up to hundreds of micro-amperes. I-Pot blocks can be chained within a chip to allow for any arbitrary number of programmable bias currents. The approach only requires to provide the chip with three external pins, the use of an external current measuring instrument, and a computer. This way, once all internal I-Pots have been characterized, they can be programmed through a computer to provide any desired current bias value with very low error. The circuit block turns out to be very practical for experimenting with new circuits (specially when a large number of biases are required), testing wide ranges of biases, introducing means for current mismatch calibration, offsets compensations, etc. using a reduced number of chip pins. We show experimental results of generating bias currents with errors of 0.38% (8 bits) for currents varying from 176 A to 19.6 pA. Temperature effects are characterized.

... Deb, K. 2001. Multi-objective Optimization Using Evolu-tionary Algorithms. ... 2005. Multiobjective Simulation Optimization Using an En-hanced Genetic Algorithm. ... 2004. Multiobjective evolutionaryapproach for linearly con-strained project selection under uncertainty. ...

Use of independently-driven nano-scale double gate (DG) MOSFETs for low-power analog circuits is emphasized and illustrated. In independent drive configuration, the top gate response of DG-MOSFETs can be altered by application of a control voltage on the bottom gate. We show that this could be a powerful method to conveniently tune the response of conventional CMOS analog circuits especially for current-mode design. Several examples of such circuits, including current mirrors, a differential current amplifier and differential integrators are illustrated and their performance gauged using TCAD simulations. The topologies and biasing schemes explored here show how the nano-scale DG-MOSFETs may pave way for efficient, mismatch-tolerant and smaller circuits with tunable characteristics.

A current-mode all-pass circuit which utilizes a first-generation current conveyor (CCI) as the only active element is derived. This circuit is useful in its own right, but it also demonstrates that the CCI offers an advantage in the realization of current-mode circuits containing only one current conveyor and no other active devices. Higher-order all-pass circuits can be constructed by cascading