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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 | /* $Id: scc.h,v 1.29 1997/04/02 14:56:45 jreuter Exp jreuter $ */ #ifndef _SCC_H #define _SCC_H #include <linux/config.h> /* selection of hardware types */ #define PA0HZP 0x00 /* hardware type for PA0HZP SCC card and compatible */ #define EAGLE 0x01 /* hardware type for EAGLE card */ #define PC100 0x02 /* hardware type for PC100 card */ #define PRIMUS 0x04 /* hardware type for PRIMUS-PC (DG9BL) card */ #define DRSI 0x08 /* hardware type for DRSI PC*Packet card */ #define BAYCOM 0x10 /* hardware type for BayCom (U)SCC */ /* DEV ioctl() commands */ enum SCC_ioctl_cmds { SIOCSCCRESERVED = SIOCDEVPRIVATE, SIOCSCCCFG, SIOCSCCINI, SIOCSCCCHANINI, SIOCSCCSMEM, SIOCSCCGKISS, SIOCSCCSKISS, SIOCSCCGSTAT, SIOCSCCCAL }; /* magic number */ #define SCC_MAGIC 0x8530 /* ;-) */ /* Device parameter control (from WAMPES) */ enum L1_params { PARAM_DATA, PARAM_TXDELAY, PARAM_PERSIST, PARAM_SLOTTIME, PARAM_TXTAIL, PARAM_FULLDUP, PARAM_SOFTDCD, /* was: PARAM_HW */ PARAM_MUTE, /* ??? */ PARAM_DTR, PARAM_RTS, PARAM_SPEED, PARAM_ENDDELAY, /* ??? */ PARAM_GROUP, PARAM_IDLE, PARAM_MIN, PARAM_MAXKEY, PARAM_WAIT, PARAM_MAXDEFER, PARAM_TX, PARAM_HWEVENT = 31, PARAM_RETURN = 255 /* reset kiss mode */ }; /* fulldup parameter */ enum FULLDUP_modes { KISS_DUPLEX_HALF, /* normal CSMA operation */ KISS_DUPLEX_FULL, /* fullduplex, key down trx after transmission */ KISS_DUPLEX_LINK, /* fullduplex, key down trx after 'idletime' sec */ KISS_DUPLEX_OPTIMA /* fullduplex, let the protocol layer control the hw */ }; /* misc. parameters */ #define TIMER_OFF 65535U /* to switch off timers */ #define NO_SUCH_PARAM 65534U /* param not implemented */ /* HWEVENT parameter */ enum HWEVENT_opts { HWEV_DCD_ON, HWEV_DCD_OFF, HWEV_ALL_SENT }; /* channel grouping */ #define RXGROUP 0100 /* if set, only tx when all channels clear */ #define TXGROUP 0200 /* if set, don't transmit simultaneously */ /* Tx/Rx clock sources */ enum CLOCK_sources { CLK_DPLL, /* normal halfduplex operation */ CLK_EXTERNAL, /* external clocking (G3RUH/DF9IC modems) */ CLK_DIVIDER, /* Rx = DPLL, Tx = divider (fullduplex with */ /* modems without clock regeneration */ CLK_BRG /* experimental fullduplex mode with DPLL/BRG for */ /* MODEMs without clock recovery */ }; /* Tx state */ enum TX_state { TXS_IDLE, /* Transmitter off, no data pending */ TXS_BUSY, /* waiting for permission to send / tailtime */ TXS_ACTIVE, /* Transmitter on, sending data */ TXS_NEWFRAME, /* reset CRC and send (next) frame */ TXS_IDLE2, /* Transmitter on, no data pending */ TXS_WAIT, /* Waiting for Mintime to expire */ TXS_TIMEOUT /* We had a transmission timeout */ }; typedef unsigned long io_port; /* type definition for an 'io port address' */ /* SCC statistical information */ struct scc_stat { long rxints; /* Receiver interrupts */ long txints; /* Transmitter interrupts */ long exints; /* External/status interrupts */ long spints; /* Special receiver interrupts */ long txframes; /* Packets sent */ long rxframes; /* Number of Frames Actually Received */ long rxerrs; /* CRC Errors */ long txerrs; /* KISS errors */ unsigned int nospace; /* "Out of buffers" */ unsigned int rx_over; /* Receiver Overruns */ unsigned int tx_under; /* Transmitter Underruns */ unsigned int tx_state; /* Transmitter state */ int tx_queued; /* tx frames enqueued */ unsigned int maxqueue; /* allocated tx_buffers */ unsigned int bufsize; /* used buffersize */ }; struct scc_modem { long speed; /* Line speed, bps */ char clocksrc; /* 0 = DPLL, 1 = external, 2 = divider */ char nrz; /* NRZ instead of NRZI */ }; struct scc_kiss_cmd { int command; /* one of the KISS-Commands defined above */ unsigned param; /* KISS-Param */ }; struct scc_hw_config { io_port data_a; /* data port channel A */ io_port ctrl_a; /* control port channel A */ io_port data_b; /* data port channel B */ io_port ctrl_b; /* control port channel B */ io_port vector_latch; /* INTACK-Latch (#) */ io_port special; /* special function port */ int irq; /* irq */ long clock; /* clock */ char option; /* command for function port */ char brand; /* hardware type */ char escc; /* use ext. features of a 8580/85180/85280 */ }; /* (#) only one INTACK latch allowed. */ struct scc_mem_config { unsigned int dummy; unsigned int bufsize; }; struct scc_calibrate { unsigned int time; unsigned char pattern; }; #ifdef __KERNEL__ enum {TX_OFF, TX_ON}; /* command for scc_key_trx() */ /* Vector masks in RR2B */ #define VECTOR_MASK 0x06 #define TXINT 0x00 #define EXINT 0x02 #define RXINT 0x04 #define SPINT 0x06 #ifdef CONFIG_SCC_DELAY #define Inb(port) inb_p(port) #define Outb(port, val) outb_p(val, port) #else #define Inb(port) inb(port) #define Outb(port, val) outb(val, port) #endif /* SCC channel control structure for KISS */ struct scc_kiss { unsigned char txdelay; /* Transmit Delay 10 ms/cnt */ unsigned char persist; /* Persistence (0-255) as a % */ unsigned char slottime; /* Delay to wait on persistence hit */ unsigned char tailtime; /* Delay after last byte written */ unsigned char fulldup; /* Full Duplex mode 0=CSMA 1=DUP 2=ALWAYS KEYED */ unsigned char waittime; /* Waittime before any transmit attempt */ unsigned int maxkeyup; /* Maximum time to transmit (seconds) */ unsigned char mintime; /* Minimal offtime after MAXKEYUP timeout (seconds) */ unsigned int idletime; /* Maximum idle time in ALWAYS KEYED mode (seconds) */ unsigned int maxdefer; /* Timer for CSMA channel busy limit */ unsigned char tx_inhibit; /* Transmit is not allowed when set */ unsigned char group; /* Group ID for AX.25 TX interlocking */ unsigned char mode; /* 'normal' or 'hwctrl' mode (unused) */ unsigned char softdcd; /* Use DPLL instead of DCD pin for carrier detect */ }; /* SCC channel structure */ struct scc_channel { int magic; /* magic word */ int init; /* channel exists? */ struct device *dev; /* link to device control structure */ struct net_device_stats dev_stat;/* device statistics */ char brand; /* manufacturer of the board */ long clock; /* used clock */ io_port ctrl; /* I/O address of CONTROL register */ io_port data; /* I/O address of DATA register */ io_port special; /* I/O address of special function port */ int irq; /* Number of Interrupt */ char option; char enhanced; /* Enhanced SCC support */ unsigned char wreg[16]; /* Copy of last written value in WRx */ unsigned char status; /* Copy of R0 at last external interrupt */ unsigned char dcd; /* DCD status */ struct scc_kiss kiss; /* control structure for KISS params */ struct scc_stat stat; /* statistical information */ struct scc_modem modem; /* modem information */ struct sk_buff_head tx_queue; /* next tx buffer */ struct sk_buff *rx_buff; /* pointer to frame currently received */ struct sk_buff *tx_buff; /* pointer to frame currently transmitted */ /* Timer */ struct timer_list tx_t; /* tx timer for this channel */ struct timer_list tx_wdog; /* tx watchdogs */ }; int scc_init(void); #endif /* defined(__KERNEL__) */ #endif /* defined(_SCC_H) */ |