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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 | /* * include/linux/fsl_devices.h * * Definitions for any platform device related flags or structures for * Freescale processor devices * * Maintainer: Kumar Gala <galak@kernel.crashing.org> * * Copyright 2004 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ #ifndef _FSL_DEVICE_H_ #define _FSL_DEVICE_H_ #include <linux/types.h> /* * Some conventions on how we handle peripherals on Freescale chips * * unique device: a platform_device entry in fsl_plat_devs[] plus * associated device information in its platform_data structure. * * A chip is described by a set of unique devices. * * Each sub-arch has its own master list of unique devices and * enumerates them by enum fsl_devices in a sub-arch specific header * * The platform data structure is broken into two parts. The * first is device specific information that help identify any * unique features of a peripheral. The second is any * information that may be defined by the board or how the device * is connected externally of the chip. * * naming conventions: * - platform data structures: <driver>_platform_data * - platform data device flags: FSL_<driver>_DEV_<FLAG> * - platform data board flags: FSL_<driver>_BRD_<FLAG> * */ enum fsl_usb2_operating_modes { FSL_USB2_MPH_HOST, FSL_USB2_DR_HOST, FSL_USB2_DR_DEVICE, FSL_USB2_DR_OTG, }; enum fsl_usb2_phy_modes { FSL_USB2_PHY_NONE, FSL_USB2_PHY_ULPI, FSL_USB2_PHY_UTMI, FSL_USB2_PHY_UTMI_WIDE, FSL_USB2_PHY_SERIAL, }; struct fsl_usb2_platform_data { /* board specific information */ enum fsl_usb2_operating_modes operating_mode; enum fsl_usb2_phy_modes phy_mode; unsigned int port_enables; }; /* Flags in fsl_usb2_mph_platform_data */ #define FSL_USB2_PORT0_ENABLED 0x00000001 #define FSL_USB2_PORT1_ENABLED 0x00000002 struct spi_device; struct fsl_spi_platform_data { u32 initial_spmode; /* initial SPMODE value */ s16 bus_num; unsigned int flags; #define SPI_QE_CPU_MODE (1 << 0) /* QE CPU ("PIO") mode */ #define SPI_CPM_MODE (1 << 1) /* CPM/QE ("DMA") mode */ #define SPI_CPM1 (1 << 2) /* SPI unit is in CPM1 block */ #define SPI_CPM2 (1 << 3) /* SPI unit is in CPM2 block */ #define SPI_QE (1 << 4) /* SPI unit is in QE block */ /* board specific information */ u16 max_chipselect; void (*cs_control)(struct spi_device *spi, bool on); u32 sysclk; }; struct mpc8xx_pcmcia_ops { void(*hw_ctrl)(int slot, int enable); int(*voltage_set)(int slot, int vcc, int vpp); }; /* Returns non-zero if the current suspend operation would * lead to a deep sleep (i.e. power removed from the core, * instead of just the clock). */ #if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND) int fsl_deep_sleep(void); #else static inline int fsl_deep_sleep(void) { return 0; } #endif #endif /* _FSL_DEVICE_H_ */ |