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1. Instruction_Binaries_Generate Instruction_Binaries_Generate Public

   generate bit stream for given RISC RV32I instructions

   Python

2. Single-Cycle-Processor Single-Cycle-Processor Public

   Single Cycle Non-Pipelined Processor for RV32I.

   Verilog 1

3. UART_Tx_Rx UART_Tx_Rx Public

   transmit instructions and receive the register file for debugging

   SystemVerilog

4. Pipelined-Processor Pipelined-Processor Public

   5-Stage Pipelined Processor for RV32I with Hazard Control and Branch Prediction.

   Verilog 1