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Pull requests: lnis-uofu/OpenFPGA
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Bump vtr-verilog-to-routing from Pull requests that update a dependency file
submodules
Pull requests that update Submodules code
7950a1b to e71ef45
dependencies
#2006
opened May 22, 2025 by
dependabot
bot
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Support IPIN connections from all four sides incoming wires of the GSB
openfpga-tools
#1946
opened Jan 25, 2025 by
ganeshgore
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Add behavior to handle unmapped muxes without constant inputs better
documentation
openfpga-bitstream
openfpga-tools
#1869
opened Oct 17, 2024 by
fkosar-ql
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Make sure net is valid before setting it as wire LUT output
openfpga-tools
#1719
opened Jun 19, 2024 by
chungshien
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Preserve escaped names
openfpga-tools
openfpga-verilog
#1589
opened Mar 4, 2024 by
alaindargelas
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[WIP] Added option to define subtile in tile_annotation section
architecture-description
flow-scripts
lang-shell
tests
#828
opened Oct 5, 2022 by
ganeshgore
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Timing annotation
architecture-description
benchmarks
flow-scripts
tests
#362
opened Jul 22, 2021 by
apond308
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Relative paths in run_modelsim.py and other changes to make Modelsim work on non-Utah machines
architecture-description
flow-scripts
#247
opened Feb 20, 2021 by
nachiket
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