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@merledu

Micro Electronics Research Laboratory

A non-profit organization fostering research on IoT, AI, and ML-based architectures leveraging the open-source RISC-V ISA.

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  1. OpenTCAM OpenTCAM Public

    An open-source Ternary Content Addressable Memory (TCAM) compiler.

    Python 28 11

  2. azadi-soc azadi-soc Public

    Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

    SystemVerilog 32 9

  3. Google-Summer-of-Code Google-Summer-of-Code Public

    Project ideas list for Google Summer of Code.

    15 2

  4. Ibtida Ibtida Public

    A basic System on a Chip (SoC) based on the Buraq core for the Internet of Things (IoT).

    Verilog 5 2

  5. TileLink TileLink Public

    TileLink Uncached Lightweight (TL-UL) implementation on Chisel.

    Scala 20 11

  6. buraq_mini buraq_mini Public

    This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

    Scala 8 6

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