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First and Last Project for STRUCTURED DESIGN OF INTEGRATED CIRCUITS discipline at UFPB. 24h clock with system verilog + Functional verification.

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clock_verilog

First Project for STRUCTURED DESIGN OF INTEGRATED CIRCUITS discipline at UFPB. 24h clock with verilog

  • Funcionalidade: relógio digital
  • Entradas: sinal de clock de 50MHz, reset
  • Saídas: 6 x 7 saídas (6 displays de 7 segment image

https://sig-arq.ufpb.br/arquivos/20232200390b125557224d341662704c1/Metodologia_Top_Down_e_Projeto_01.pptx.pdf

Part 2 - Functional verification (Modelsim)

Testbench implementation

image

  • Modelsim screenshot

Docs:

OBS: There is a known error at modelsim simulation.
  • image
  • For some reason, the first "run -all" detects a bug.
  • image
  • Just click at continue to continue the expected simulation

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First and Last Project for STRUCTURED DESIGN OF INTEGRATED CIRCUITS discipline at UFPB. 24h clock with system verilog + Functional verification.

Topics

verilog systemverilog testbench system-verilog functional-verification 24h-clock

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