WIP: starfive/visionfive2: main + sbi

Signed-off-by: Daniel Maslowski <info@orangecms.org>
oreboot · orangecms · Jun 17, 2023 · Jun 18, 2023 · Jan 29, 2024 · Jan 13, 2024
commit 7fd02924f67936ca69f521f285de5c7def66da04
diff --git a/src/mainboard/starfive/visionfive2/bt0/Cargo.toml b/src/mainboard/starfive/visionfive2/bt0/Cargo.toml
@@ -10,6 +10,7 @@ edition = "2021"
 embedded-hal = "1.0.0"
 embedded-hal-nb = "1.0.0"
 fdt = "0.1.4"
+jh71xx-hal = { version = "0.1", features = ["rt"] }
 jh71xx-pac = "0.3"
 nb = "1"
 riscv = "0.10.1"
@@ -18,7 +19,4 @@ spin = "0.9"
 layoutflash = { path = "../../../../lib/layoutflash" }
 log = { path = "../../../../lib/log" }
 soc = { path = "../../../../soc", package = "oreboot-soc", features = ["starfive_jh7110"] }
-
-[dependencies.jh71xx-hal]
-version = "0.1"
-features = ["rt"]
+starfive-visionfive2-lib = { path = "../lib" }
diff --git a/src/mainboard/starfive/visionfive2/bt0/build.rs b/src/mainboard/starfive/visionfive2/bt0/build.rs
@@ -7,7 +7,7 @@ const LINKERSCRIPT_FILENAME: &str = "link-visionfive2-bt0.ld";
 
 // NOTE: The SRAM is called "L2 LIM", documented here:
 // https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/u74_memory_map.html
-const FLASH: &[u8] = b"
+const LINKERSCRIPT: &[u8] = b"
 OUTPUT_ARCH(riscv)
 ENTRY(_start)
 MEMORY {
@@ -50,7 +50,7 @@ fn main() {
     let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
     File::create(out.join(LINKERSCRIPT_FILENAME))
         .unwrap()
-        .write_all(FLASH)
+        .write_all(LINKERSCRIPT)
         .unwrap();
     println!("cargo:rustc-link-search={}", out.display());
 }
diff --git a/src/mainboard/starfive/visionfive2/bt0/src/ddrcsr.rs b/src/mainboard/starfive/visionfive2/bt0/src/ddrcsr.rs
@@ -1,6 +1,7 @@
 use crate::ddrlib::*;
-use crate::init::{self, read32, udelay, write32};
+use crate::init::{self, read32, write32};
 use crate::pac;
+use starfive_visionfive2_lib::udelay;
 
 const FREQ_CHANGE: usize = 0x0001;
 const FREQ_CHANGE_ACK: usize = 0x0002;

diff --git a/src/mainboard/starfive/visionfive2/bt0/src/dram.rs b/src/mainboard/starfive/visionfive2/bt0/src/dram.rs
@@ -3,8 +3,9 @@ use soc::starfive::jh7110::pac;
 use crate::ddr_start::start;
 use crate::ddrcsr::omc_init;
 use crate::ddrphy::{train, util};
-use crate::init::{self, read32, udelay, write32};
+use crate::init::{self, read32, write32};
 use crate::pll;
+use starfive_visionfive2_lib::udelay;
 
 // TODO: support 1G
 #[cfg(not(any(dram_size = "2G", dram_size = "4G", dram_size = "8G")))]

diff --git a/src/mainboard/starfive/visionfive2/bt0/src/init.rs b/src/mainboard/starfive/visionfive2/bt0/src/init.rs
@@ -43,14 +43,6 @@ pub fn set_bit(reg: usize, bit: u32) {
     }
 }
 
-const CLINT_BASE: usize = 0x0200_0000;
-const CLINT_MTIMER: usize = CLINT_BASE + 0xbff8;
-
-pub fn udelay(t: usize) {
-    let curr_time = read32(CLINT_MTIMER);
-    while read32(CLINT_MTIMER) < (curr_time + 4 * t as u32) {}
-}
-
 pub const DDR_CTRL_BASE: usize = 0x1570_0000;
 pub const DDR_SEC_CTRL_BASE: usize = DDR_CTRL_BASE + 0x1000;
 

diff --git a/src/mainboard/starfive/visionfive2/bt0/src/main.rs b/src/mainboard/starfive/visionfive2/bt0/src/main.rs
@@ -17,9 +17,10 @@ use core::{
     panic::PanicInfo,
     ptr::{self, addr_of, addr_of_mut},
 };
-use init::{dump_block, read32, write32};
 use riscv::register::mhartid;
 use riscv::register::{marchid, mimpid, mvendorid};
+use starfive_visionfive2_lib::{dump_block, read32, udelay, write32};
+use uart::JH71XXSerial;
 
 use fdt::Fdt;
 

diff --git a/src/mainboard/starfive/visionfive2/bt0/src/pll.rs b/src/mainboard/starfive/visionfive2/bt0/src/pll.rs
@@ -1,6 +1,7 @@
 use soc::starfive::jh7110::pac;
 
-use crate::init::{self, read32, udelay, write32};
+use crate::init;
+use starfive_visionfive2_lib::{read32, udelay, write32};
 
 // see `boot/arch/riscv/cpu/jh7110/pll.c` `pll_set_rate`
 // NOTE: The order may be irrelevant, which would allow for simplification.

diff --git a/src/mainboard/starfive/visionfive2/lib/src/lib.rs b/src/mainboard/starfive/visionfive2/lib/src/lib.rs
@@ -113,7 +113,7 @@ pub fn resume_nonboot_harts() {
 
 pub fn udelay(t: usize) {
     let curr_time = read32(CLINT_MTIMER);
-    while read32(CLINT_MTIMER) < (curr_time + 4 * t as u32) {}
+    while read32(CLINT_MTIMER) < (curr_time + 2 * t as u32) {}
 }
 
 pub fn get_mtime() -> u64 {

diff --git a/src/mainboard/starfive/visionfive2/main/Cargo.toml b/src/mainboard/starfive/visionfive2/main/Cargo.toml
@@ -1,5 +1,3 @@
-# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
-
 [package]
 name = "starfive-visionfive2-main"
 version = "0.1.0"
@@ -13,8 +11,16 @@ embedded-hal = "1.0.0"
 embedded-hal-nb = "1.0.0"
 nb = "1"
 riscv = "0.10.1"
+rustsbi = "0.3.2"
+sbi-spec = "0.0.4"
 spin = "0.9"
 
+log = { path = "../../../../lib/log" }
+oreboot-arch = { path = "../../../../arch", features = ["riscv64"] }
+oreboot_compression = { path = "../../../../lib/compression" }
+
+starfive-visionfive2-lib = { path = "../lib" }
+
 [dependencies.soc]
 path = "../../../../soc"
 package = "oreboot-soc"

diff --git a/src/mainboard/starfive/visionfive2/main/build.rs b/src/mainboard/starfive/visionfive2/main/build.rs
@@ -3,54 +3,55 @@ use std::fs::File;
 use std::io::Write;
 use std::path::PathBuf;
 
-const FLASH: &[u8] = b"
+const LINKERSCRIPT_FILENAME: &str = "link-visionfive2-main.ld";
+
+const LINKERSCRIPT: &[u8] = b"
 OUTPUT_ARCH(riscv)
 ENTRY(_start)
 MEMORY {
-    SRAM : ORIGIN = 0x40000000, LENGTH = 128k
+    DRAM : ORIGIN = 0x80000000, LENGTH = 512k
 }
 SECTIONS {
     .head : {
         *(.head.text)
         KEEP(*(.debug))
         KEEP(*(.bootblock.boot))
-    } > SRAM
+    } > DRAM
     .text : {
         KEEP(*(.text.entry))
         *(.text .text.*)
-    } > SRAM
+        . = ALIGN(8);
+    } > DRAM
+    .bss : {
+        _sbss = .;
+        *(.bss .bss.*);
+        _ebss = .;
+    } > DRAM
+
     .rodata : ALIGN(4) {
-        srodata = .;
         *(.rodata .rodata.*)
-        *(.srodata .srodata.*)
         . = ALIGN(4);
-        erodata = .;
-    } > SRAM
+    } > DRAM
     .data : ALIGN(4) {
-        sdata = .;
-        *(.data .data.*)
-        *(.sdata .sdata.*)
+        _sdata = .;
+        *(.data .data.*);
         . = ALIGN(4);
-        edata = .;
-    } > SRAM
-    sidata = LOADADDR(.data);
-    .bss (NOLOAD) : ALIGN(4) {
-        *(.bss.uninit)
-        sbss = .;
-        *(.bss .bss.*)
-        *(.sbss .sbss.*)
-        ebss = .;
-    } > SRAM
+        _edata = .;
+    } > DRAM
+    _sidata = LOADADDR(.data);
+
     /DISCARD/ : {
         *(.eh_frame)
+        *(.debug_*)
+        *(.comment*)
     }
 }";
 
 fn main() {
     let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
-    File::create(out.join("link-visionfive2-main.ld"))
+    File::create(out.join(LINKERSCRIPT_FILENAME))
         .unwrap()
-        .write_all(FLASH)
+        .write_all(LINKERSCRIPT)
         .unwrap();
     println!("cargo:rustc-link-search={}", out.display());
 }