Fix bit shift in AHB1 register for CRC enable/reset/sleep-mode bits, STM32L4x3.svd patch #517
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Discovered when attempting to enable CRC hardware module.
```rust
let crc_guy = dp.CRC.constrain(&mut rcc.ahb1);
```
CRC output would be 0. Found with debugger that the enable bit was not
being set in rcc.ahb1 power enable register. Other peripherals in the
register (DMA1/2) could be enabled and the remaining bits in the
register are not writable.
Tested against the following code provided by STM32CubeMX, in which the
CRC module is functional.
Source: CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h
```
```
- STM32L43xxx... Reference Manual RM0394 Rev 4. Sections 6.4.9, 6.4.15, 6.4.21
- Bug Verified/Fixed/Tested on STM32L433 (Nucleo-L433RC-P)
adamgreig
requested changes
Mar 23, 2021
Co-authored-by: Adam Greig <adam@adamgreig.com>
adamgreig
requested changes
Mar 27, 2021
There was a problem hiding this comment.
Sorry, looks like my indentation wasn't quite right in that suggested change - the new content had been indented with 4 spaces per tab, so when we combined the sections they were indented underneath the existing APB1ENR1 register and that's why the CI failed.
Co-authored-by: Adam Greig <adam@adamgreig.com>
adamgreig
approved these changes
Mar 28, 2021
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Discovered when attempting to enable CRC hardware module.
CRC output would be 0. Found with debugger that the enable bit was not
being set in rcc.ahb1 power enable register. Other peripherals in the
register (DMA1/2) could be enabled and the remaining bits in the
register are not writable.
Tested against the following code provided by STM32CubeMX, in which the
CRC module is functional.
Sources
CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h
STM32L43xxx... Reference Manual RM0394 Rev 4. Sections 6.4.9, 6.4.15, 6.4.21
Bug Verified/Fixed/Tested on STM32L433 (Nucleo-L433RC-P)