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Merged
merged 1 commit into from
Aug 16, 2021
Merged

rework OCxM fields in timers #546

merged 1 commit into from
Aug 16, 2021

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burrbull
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@burrbull burrbull commented Apr 24, 2021 •
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изображение

MP1 is not covered by this PR

Closes #541

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@burrbull burrbull changed the title rework CC1M field in timers rework OCxM fields in timers Apr 24, 2021
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@adamgreig adamgreig mentioned this pull request Apr 24, 2021
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bors retry

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bors bot commented Apr 25, 2021

🔒 Permission denied

Existing reviewers: click here to make burrbull a reviewer

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is rustfmt broken?

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@adamgreig I think it is ready.

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Thank you! I will try and review in the next few days if possible.

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jorgeig-space pushed a commit to munin-space/stm32-rs that referenced this pull request Jun 29, 2021
Change OC?M nomenclature to match stm32-rs#546
a34260a
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Rebased.

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@adamgreig Rebased

richardeoin
richardeoin previously approved these changes Aug 3, 2021
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This PR is needed to get the H7 HAL building again after #540, but with this PR it builds just fine.

One of the bigger changes in this PR is the change in the name of the field of CCRx registers from CCRx to just CCR in those families where this wasn't the case already. I'm generally in favour of this for simplicity/consistency, although it is a deviation from the RM in the cases I've checked.

I had a look through the F[0134], G[04] and L[04] HALs to see where those HALs will be affected. There's three that will be affected.

  • stm32f0xx-hal here here
  • stm32f3xx-hal here and further down...
  • stm32l4xx-hal here

In all cases this PR makes the CCR naming more consistent between timers - which is a good thing imo!

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adamgreig commented Aug 15, 2021 •
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Thanks so much for getting through all this and sorting it all out. Sorry it's taken so long to review.

I've checked over the memory map diff (so haven't yet covered all the enumerated values...) and noticed the following issues created by these changes:

  • A lot of CCR2/CCR3/CCR4 registers now have a description of "capture/compare register 1", maybe all CCRs could have the number removed so they can share a description. Same issue with the CCR field inside being "Capture/compare 1 value".
  • F102: TIM13/14 gain a CR2 register that's not in the RM
  • F102/F107: TIM13/14 CCMR1 loses OC1FE field, but it's in the RM
  • F215/F217: TIM5's OR is renamed from TIM5_OR to TIM2_OR (and incidentally field is named IT4_RMP but should be TI4_RMP, though that's already wrong in the existing SVDs)
  • F301: has TIM3 and TIM4 but shouldn't (not introduced by this PR)
  • F302/F303: TIM17 gains a new option register OR that doesn't exist (but has no fields; TIM16 also has an empty OR which should have a field)
  • F373: TIM5 has an OR but shouldn't; its field changed from IT4_RMP to ITR1_RMP but neither is right
  • F412/F413: TIM12 has gained CR2, but it's not in the RM
  • F412/F413: TIM12 CCMR1 IC2F has shrunk from 4 to 3 bits, but 4 bits is correct
  • F745/F750/F765/F7x6/F7x7/F7x9: TIM4 and TIM5 have gained the same OR1 and OR2 from TIM3 described as "TIM3 Option Register 1/2", but neither TIM3 nor TIM4 should have any ORs, and TIM5 should have TIM5_OR instead, with TI4_RMP field
  • G4 (all): TIM1/3/4/15/16 CNT is now 20 bits, but should be 16 (ARR changed 16->20 which is correct)
  • G4 (all): TIM2: CNT is now 31 bits, but perhaps it should be 32 and alias the UIFCPY field in bit position 31? by default bit 31 is part of CNT field, and that's what you'll want most of the time to use it as a 32-bit timer, while UIFCPY is a relatively niche use of a copy of the UIF flag
  • H7 (all): TIM17's TIM17_AF1 is renamed to TIM16_AF1, and TIM17_TISEL to TIM16_TISEL
  • L4R9: The change to having CNT_H etc for the 32-bit fields, present even on non-32-bit timers, is a bit confusing compared to how it's done everywhere else, but I think this can just be fixed in a separate PR
  • L552: TIM4 and TIM5 have gained OR1 and OR2 but shouldn't have them (both secure and non-secure)
  • L552: TIM7 CCR2 has moved from 0x38 to 0x28, where it overlaps PSC, but it shouldn't exist at all (both secure and non-secure)
  • L552: TIM17 OR2 bit 8 has incorrectly renamed from BKDF1BK2E (correct) to BKDF1BK1E (incorrect) (both secure and non-secure)
  • WB55: TIM17 CR1's fields all deleted and incorrectly replaced by TIM17_AF1's fields
  • WB55: TIM17 DIER moved to correct location but also contains AF1's fields instead of correct DIER fields
  • WL5 (all): TIM17 option and alternate function register renamed to TIM16

On the whole it is mostly option registers being annoying and TIM17 being annoying. I hope most are fairly easy to fix. Some might be better served by future PRs instead though, up to you. I think the more severe issues here probably need fixing before merging, but we don't need to fix everything before merging this PR.

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burrbull commented Aug 16, 2021 •
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  • A lot of CCR2/CCR3/CCR4 registers now have a description of "capture/compare register 1", maybe all CCRs could have the number removed so they can share a description. Same issue with the CCR field inside being "Capture/compare 1 value".

  • F102: TIM13/14 gain a CR2 register that's not in the RM

  • F102/F107: TIM13/14 CCMR1 loses OC1FE field, but it's in the RM

  • F215/F217: TIM5's OR is renamed from TIM5_OR to TIM2_OR (and incidentally field is named IT4_RMP but should be TI4_RMP, though that's already wrong in the existing SVDs)

  • F301: has TIM3 and TIM4 but shouldn't (not introduced by this PR)

  • F302/F303: TIM17 gains a new option register OR that doesn't exist (but has no fields; TIM16 also has an empty OR which should have a field)

  • F373: TIM5 has an OR but shouldn't; its field changed from IT4_RMP to ITR1_RMP but neither is right

  • F412/F413: TIM12 has gained CR2, but it's not in the RM

  • F412/F413: TIM12 CCMR1 IC2F has shrunk from 4 to 3 bits, but 4 bits is correct

  • F745/F750/F765/F7x6/F7x7/F7x9: TIM4 and TIM5 have gained the same OR1 and OR2 from TIM3 described as "TIM3 Option Register 1/2", but neither TIM3 nor TIM4 should have any ORs, and TIM5 should have TIM5_OR instead, with TI4_RMP field

  • G4 (all): TIM1/3/4/15/16 CNT is now 20 bits, but should be 16 (ARR changed 16->20 which is correct)

  • G4 (all): TIM2: CNT is now 31 bits, but perhaps it should be 32 and alias the UIFCPY field in bit position 31? by default bit 31 is part of CNT field, and that's what you'll want most of the time to use it as a 32-bit timer, while UIFCPY is a relatively niche use of a copy of the UIF flag

  • H7 (all): TIM17's TIM17_AF1 is renamed to TIM16_AF1, and TIM17_TISEL to TIM16_TISEL

  • L4R9: The change to having CNT_H etc for the 32-bit fields, present even on non-32-bit timers, is a bit confusing compared to how it's done everywhere else, but I think this can just be fixed in a separate PR

  • L552: TIM4 and TIM5 have gained OR1 and OR2 but shouldn't have them (both secure and non-secure)

  • L552: TIM7 CCR2 has moved from 0x38 to 0x28, where it overlaps PSC, but it shouldn't exist at all (both secure and non-secure)

  • L552: TIM17 OR2 bit 8 has incorrectly renamed from BKDF1BK2E (correct) to BKDF1BK1E (incorrect) (both secure and non-secure)

  • WB55: TIM17 CR1's fields all deleted and incorrectly replaced by TIM17_AF1's fields

  • WB55: TIM17 DIER moved to correct location but also contains AF1's fields instead of correct DIER fields

  • WL5 (all): TIM17 option and alternate function register renamed to TIM16

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Thanks for the quick response, all the updates look good.

bors merge

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bors bot commented Aug 16, 2021

Build succeeded:

@bors bors bot merged commit 5e75142 into stm32-rs:master Aug 16, 2021
richardeoin added a commit to richardeoin/stm32-rs that referenced this pull request Aug 17, 2021
@richardeoin
Resolve small breakage in OCxM fields for stm32h735 in stm32-rs#546
8b467f5 
After 0cb0f60 the peripheral patches for the
OCxM fields were no longer applied for these parts. This PR fixes that.

* Add `peripherals/tim/v2/ccm.yaml` that appeared during the refactor but wasn't
added to the device
* Remove duplicate include of `common_patches/tim/tim_ccr.yaml`
bors bot added a commit that referenced this pull request Aug 17, 2021
@bors @richardeoin
Merge #596
dd80b13 
596: Resolve small breakage in OCxM fields for stm32h735 in #546 r=adamgreig a=richardeoin

After 0cb0f60 the peripheral patches for the OCxM fields were no longer applied for these parts. This PR fixes that.

* Add `peripherals/tim/v2/ccm.yaml` that appeared during the refactor but wasn't added to this device
* Remove duplicate include of `common_patches/tim/tim_ccr.yaml`

Co-authored-by: Richard Meadows <962920+richardeoin@users.noreply.github.com>
@maximeborges maximeborges mentioned this pull request Aug 18, 2021
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@burrbull burrbull deleted the timers branch August 14, 2022 08:45
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F7 TIMx CCMRx_Output OCxM
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