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Fix various issues with STM32L562 #715

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Merged
merged 3 commits into from
Jul 3, 2022
Merged

Fix various issues with STM32L562 #715

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c8f945d
add missing fields for DMA registers in STM32L562
sphw Apr 5, 2022
287f91e
merge GTZC MPCBB VCTZR registers into array
sphw Apr 5, 2022
7548836
L562: delete extra MA register from CNDTR and CCR registers
adamgreig Jul 3, 2022
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174 changes: 172 additions & 2 deletions devices/stm32l562.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@ _modify:
fpuPresent: "true"
nvicPrioBits: 3
vendorSystickConfig: "false"

FMC:
_strip:
- "FMC_"
Expand All @@ -29,10 +28,15 @@ PKA:
GTZC_MPCBB1:
_strip:
- "MPCBB1_"

_array:
"VCTR*":
name: VCTR%s
GTZC_MPCBB2:
_strip:
- "MPCBB2_"
_array:
"VCTR*":
name: VCTR%s

GTZC_TZIC:
_strip:
Expand All @@ -42,6 +46,172 @@ GTZC_TZSC:
_strip:
- "TZSC_"

"DMA[1-2]":
"CNDTR[2-4]":
_add:
NDT:
description: Number of data to transfer
bitOffset: 0
bitWidth: 18
_delete:
- MA
"CNDTR[6-8]":
_add:
NDT:
description: Number of data to transfer
bitOffset: 0
bitWidth: 16
_delete:
- MA

# exclude CCR1 and CCR5, since they already contains the correct regs
"CCR[2-4]":
_add:
MEM2MEM:
description: Memory to memory mode
bitOffset: 14
bitWidth: 1
PL:
description: Channel priority level
bitOffset: 12
bitWidth: 2
MSIZE:
description: Memory size
bitOffset: 10
bitWidth: 2
PSIZE:
description: Peripheral size
bitOffset: 8
bitWidth: 2
MINC:
description: Memory increment mdoe
bitOffset: 7
bitWidth: 1
PINC:
description: Peripheral increment mode
bitOffset: 7
bitWidth: 1
CIRC:
description: Ciruclar mode
bitOffset: 5
bitWidth: 1
DIR:
description: Data transfer direction
bitOffset: 4
bitWidth: 1
TEIE:
description: Transfer error interupt enable
bitOffset: 3
bitWidth: 1
HTIE:
description: Half transfer interrupt enable
bitOffset: 2
bitWidth: 1
TCIE:
description: Transfer complete interrupt enable
bitOffset: 1
bitWidth: 1
EN:
description: Channel enable
bitOffset: 0
bitWidth: 1
DBM:
description: double-buffer mode
bitOffset: 15
bitWidth: 1
CT:
description: Current target memory of DMA transfer in double-bufer mode
bitOffset: 16
bitWidth: 1
SECM:
bitOffset: 17
bitWidth: 1
SSEC:
bitOffset: 18
bitWidth: 1
DSEC:
bitOffset: 19
bitWidth: 1
PRIV:
description: privileged mode
bitOffset: 20
bitWidth: 1
_delete:
- MA
"CCR[6-8]":
_add:
MEM2MEM:
description: Memory to memory mode
bitOffset: 14
bitWidth: 1
PL:
description: Channel priority level
bitOffset: 12
bitWidth: 2
MSIZE:
description: Memory size
bitOffset: 10
bitWidth: 2
PSIZE:
description: Peripheral size
bitOffset: 8
bitWidth: 2
MINC:
description: Memory increment mdoe
bitOffset: 7
bitWidth: 1
PINC:
description: Peripheral increment mode
bitOffset: 7
bitWidth: 1
CIRC:
description: Ciruclar mode
bitOffset: 5
bitWidth: 1
DIR:
description: Data transfer direction
bitOffset: 4
bitWidth: 1
TEIE:
description: Transfer error interupt enable
bitOffset: 3
bitWidth: 1
HTIE:
description: Half transfer interrupt enable
bitOffset: 2
bitWidth: 1
TCIE:
description: Transfer complete interrupt enable
bitOffset: 1
bitWidth: 1
EN:
description: Channel enable
bitOffset: 0
bitWidth: 1
DBM:
description: double-buffer mode
bitOffset: 15
bitWidth: 1
CT:
description: Current target memory of DMA transfer in double-bufer mode
bitOffset: 16
bitWidth: 1
SECM:
bitOffset: 17
bitWidth: 1
SSEC:
bitOffset: 18
bitWidth: 1
DSEC:
bitOffset: 19
bitWidth: 1
PRIV:
description: privileged mode
bitOffset: 20
bitWidth: 1
_delete:
- MA

_include:
- common_patches/dma_interrupt_names.yaml
- ../peripherals/gpio/gpio_l5.yaml
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