digital-design-and-computer-organization

Here are 13 public repositories matching this topic...

player400 / pi

My very own CPU architecture! Emulator availible!

cpp digital hardware assembly architecture emulation assembly-language computer-architecture microcode emulators instruction-set-architecture digital-design cpp-programming hardware-design emulator-development digital-design-and-computer-organization

Updated Jun 11, 2025
C++

ArvinDelavari / Digital-Circuits-Verilog

Star

Sample Verilog codes for digital circuits

cpu vscode verilog computer-architecture hdl risc-v iverilog digital-design hardware-description-language cpu-design digital-design-and-computer-organization

Updated Oct 22, 2023
Verilog

DopeBiscuit / IEEE-Digital-IC-Design

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This repo is for my IEEE ASU Student Branch Digital IC Design workshop, an introduction to digital design using Verilog, this is a documentation of my tasks.

logic-design verilog-project digital-design-and-computer-organization

Updated Oct 10, 2023
Verilog

Prajna-Ramamurthy / Pseudo-Random-Binary-Sequence-Generator

Star

Digital Design and Computer Organisation Mini-project

arm fpga project verilog college-project digital-design computer-organization prbs-generator mini-project sequence-generation pseudo-random-generator field-programmable-gate-arrays verilog-project sequence-generator prbs ddco arm7tdmi digital-design-and-computer-organization binary-sequence-generator

Updated Aug 7, 2023
Verilog

VishalS-HK / DDCO-Lab-UE21CS251A

Star

A Repo that contains the source code for Digital Design and Computer Organisation course.

verilog icarus-verilog digital-design-and-computer-organization

Updated Jan 4, 2023
Verilog

SpencerDeMera / 8-Bit-ALU-Circuit

Star

This project is my design of a basic ALU that can perform addition, subtraction, and bitwise logic operations. This project was designed in Logisim Evolution and implemented with TTL logic chips on breadboards.

digital-design logic-design digital-design-and-computer-organization

Updated Jun 27, 2023

a-gafiyatullin / digital-design

Star

🖥️ Digital Design and Computer Architecture

verilog computer-architecture system-verilog digital-design digital-design-and-computer-organization

Updated Jul 22, 2023
SystemVerilog

seckinalp / Bilkent_CS223_Digital_Desing_Computer_Architecture

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My solutions to Bilkent University Digital Design Course which focuses on SystemVerilog and computer architecture.

systemverilog bilkent digital-design-and-computer-organization

Updated Feb 29, 2024

karthikeyaneti / verilog_learning

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A collection of Verilog implementations and exercises covering fundamental digital design concepts that I have worked on.

rtl verilog digital-design digital-design-and-computer-organization

Updated Jun 6, 2025
Verilog

Parsley97 / LF-Building-a-RISC-V-CPU-Core

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My implementation of RISC-V CPU Core using TL-Verilog

verilog risc-v digital-design-and-computer-organization

Updated Sep 5, 2024
TL-Verilog

OccupyMars2025 / Digital-Design-with-an-introduction-to-the-Verilog-HDL

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by M. Morris Mano, Michael D. Ciletti. 5th Edition

digital-design-and-computer-organization

Updated Apr 6, 2023

Pranavh-2004 / 64KB_RAM_iverilog

Star

PESU Sem 3: Mini project for Digital Design and Computer Organization

ram verilog hdl modular-design memory-design digital-design-and-computer-organization

Updated Nov 17, 2024
Verilog

Awais-Asghar / Single-Cycle-RISC-V-Processor-Implemented-on-FPGA

Star

An FPGA-based single-cycle RISC-V processor (RV32I) implemented in SystemVerilog. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. This project is ideal for learning computer architecture, digital design, and RISC-V ISA implementation.

fpga vivado computer-architecture system-verilog risc-v cpu-architecture processor-design single-cycle-processor digital-design-and-computer-organization rv32i-processor

Updated Jul 21, 2025
SystemVerilog

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digital-design-and-computer-organization

Here are 13 public repositories matching this topic...

player400 / pi

ArvinDelavari / Digital-Circuits-Verilog

DopeBiscuit / IEEE-Digital-IC-Design

Prajna-Ramamurthy / Pseudo-Random-Binary-Sequence-Generator

VishalS-HK / DDCO-Lab-UE21CS251A

SpencerDeMera / 8-Bit-ALU-Circuit

a-gafiyatullin / digital-design

seckinalp / Bilkent_CS223_Digital_Desing_Computer_Architecture

karthikeyaneti / verilog_learning

Parsley97 / LF-Building-a-RISC-V-CPU-Core

OccupyMars2025 / Digital-Design-with-an-introduction-to-the-Verilog-HDL

Pranavh-2004 / 64KB_RAM_iverilog

Awais-Asghar / Single-Cycle-RISC-V-Processor-Implemented-on-FPGA

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