Cardinal NIC and Chip Multiprocessor
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Dec 1, 2021 - Verilog
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innovus
Here are 8 public repositories matching this topic...
DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino
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Jan 16, 2023 - Verilog
An application using Cadence IC Package
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Feb 12, 2023 - Verilog
Detailed routed RT01 and other testcases with Innovus NanoRoute; includes RT01 random blockages. Example routes include CLK paths avoiding all blockages and connecting all DFF pins. All modules are designed with the GSCLK45nm standard cell library. Note that NanoRoute is typically used for routing std cell placements; in this case, custom top-level
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Jul 16, 2023
Undegraduate Capstone Project - Spring'21 (VIT University).
cryptography computer-architecture verilog-hdl risc-v digital-logic-design bitmanipulation asic-design innovus
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Aug 6, 2021 - Verilog
This repository is about the main project of the course "VLSI System Design". This course is part of my undergraduate studies on University of Thessally - ECE Department located in Volos, Greece.
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Nov 25, 2024 - Verilog
Simulation, Logical and Physical Syntesis of the RISC-V Steel Core using Cadence EDA tools.
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Jan 15, 2025 - Verilog
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