OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description and software programming languages

A textbook on understanding system on chip design

⚙️ 基于 Zynq-7 全可编程 SoC 的设计

A textbook on system on chip design using Arm Cortex-A

A reference book on System-on-Chip Design

Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

SystemVerilog implementation of a multi-bank memory as part of "[F23] Digital Circuit Design" course

Entries for the 2023 5th National College Student Integrated Circuit EDA Elite Challenge. SoC chip physical layout static IR drop prediction project based on methods such as image processing and NLP unsupervised learning.

BDD Gherkin implementation in native SystemVerilog, based on UVM.

Digital VLSI Soc-Physical Design (Picorv32)

Репозиторий пэт проекта 8-и битного процессора

Workspace for CSE4178 - Basic SoC Design course (기초SOC설계), Fall 2020, Sogang University

ECE2300: Digital Logic and Computer Organization

End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.