Bus bridges and other odds and ends
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Jan 23, 2025 - Verilog
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xilinx-vivado
Here are 181 public repositories matching this topic...
Repurposing existing HDL tools to help writing better code
python vim language-server vhdl verilog xilinx syntax-checker systemverilog hdl modelsim questasim ghdl xilinx-vivado lsp-server coc-nvim vim-ale vivado-simulator mentor-msim hdl-checker emacs-lsp
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Jun 6, 2024 - Python
Xilinx Virtual Cable Server for Raspberry Pi
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Mar 14, 2022 - C
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
simulator encoder decoder priority verilog xilinx testbenches multiplexer comparator adder system-verilog xilinx-vivado half-adder traffic-light-controller full-adder ripple-adder look-ahead-adder
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Oct 2, 2019 - Verilog
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
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Jul 9, 2023 - Verilog
USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
fpga usb rtl verilog wireshark xilinx-vivado usb-debugging usb-scanning artix-7 usb2 usb-analyzer usb-sniffer lambdaconcept-usb2sniffer-hardware
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Jun 6, 2020 - Verilog
This cybersecurity guide provides a comprehensive approach to hardware obfuscation using LambdaConcept's PCIe Screamer Squirrel DMA board. It is intended for educational and research purposes only.
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Jan 28, 2025
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
calculator vhdl matrix-multiplication verilog xilinx hardware-designs xilinx-fpga low-level-programming xilinx-ise xilinx-vivado ic-design
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Aug 12, 2017 - Verilog
中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
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Jun 24, 2017 - Verilog
Extremely basic CortexM0 SoC based on ARM DesignStart Eval
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Oct 8, 2018 - Verilog
This repository contains all labs done as a part of the Embedded Logic and Design course.
c arm vhdl embedded-systems verilog xilinx vivado logic-programming zedboard verilog-hdl xilinx-fpga logic-circuit xilinx-vivado embedded-c vhdl-code pmod xilinx-sdk verilog-programs verilog-project embedded-logic
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Jun 10, 2018
SPI ELF bootloader for Xilinx Microblaze processors
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Oct 17, 2017 - C
experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
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Dec 14, 2023 - Tcl
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
spi-interface fpga spi altera verilog-hdl xilinx-fpga xilinx-vivado verilog-components axi verilog-snippets spi-hdl spi-ip-core spi-pld spi-fpga verilog-spi axi-interfaces bit-oriented-spi soft-spi hard-spi dragster-spi
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Nov 21, 2017 - Verilog
Trying to get a new skill
digital electronics rtl verilog xilinx vivado altera modelsim testbench xilinx-vivado quartus-prime gowin
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Dec 31, 2024 - Verilog
The project uses a Xilinx Artix-7 FPGA on a Digilent Basys 3 board to design a clock whose seconds, minutes, & hours are displayed on a Quad 7-segment display & can also be displayed on a vga display. Picoblaze processor is used to control the Analog & Digital displays of the clock.
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Mar 17, 2019 - VHDL
A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.
embedded-systems fpga-soc zedboard verilog-hdl xilinx-fpga xilinx-vivado zynq-7000 digital-oscilloscope
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Jul 30, 2020
Bazel rules for Xilinx Vivado
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Sep 1, 2022 - Python
Repository to store all design and testbench files for Senior Design
rtl verilog systemverilog hardware-designs testbenches xilinx-vivado hardware-security physical-unclonable-functions ring-oscillator
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Apr 16, 2020 - Verilog
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