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yacc
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Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
productivity parser formatter analysis style-linter linter language-server-protocol syntax-tree lexer yacc systemverilog hacktoberfest lsp-server systemverilog-parser systemverilog-developer sv-lrm verible
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May 28, 2025 - C++
The fast scanner generator for Java™ with full Unicode support
java flex parsing cup scanner regexp tokenizer grammar maven-plugin bazel-rules lexer yacc lexer-generator nfa dfa lexical-analyzer dfa-minimization scanner-generator
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Jan 1, 2025 - Java
como-lang-ng is now ana-lang, located at https://github.com/analang/ana
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Aug 8, 2019 - C
A compiler that accepts any valid program written in C. It is made using Lex and Yacc. Returns a symbol table, parse tree, annotated syntax tree and intermediate code.
c parser frontend compiler ast lex syntax-tree lexical-analysis yacc symbol-table semantic-analysis compiler-construction intermediate-code-generation parse-tree
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Apr 24, 2023 - Yacc
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
cli cpp eda lex verilog yacc vlsi fan-out atpg electronic-design-automation fault-simulation sequential-circuits stuck-at combinational-circuits test-pattern vlsi-testing
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Nov 20, 2023 - Verilog
Cyrus: A high-performance, statically-typed, manually memory-managed, mid-level programming language. (heavily under development)
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May 31, 2025 - Rust
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