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    Sequence v31.8

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    Ashok Jangra
    The document describes the power-up sequence from G3 state to S0 state for the C51/MCP51 microcontroller. It shows that the various power planes and clocks are enabled in a specific sequence to ensure proper powering and initialization of the device. First, the reset and crystal clock signals are activated along with the primary power supplies. Then each subsequent block such as the CPU, PLLs, and peripheral power planes are enabled only after the previous block is stable. This staged powering approach helps avoid faults or errors during power-on of the integrated circuit.

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    Download as PDF, TXT or read online from Scribd

    Sequence v31.8

    Uploaded by

    Ashok Jangra
    37 views1 page
    The document describes the power-up sequence from G3 state to S0 state for the C51/MCP51 microcontroller. It shows that the various power planes and clocks are enabled in a specific sequence to ensure proper powering and initialization of the device. First, the reset and crystal clock signals are activated along with the primary power supplies. Then each subsequent block such as the CPU, PLLs, and peripheral power planes are enabled only after the previous block is stable. This staged powering approach helps avoid faults or errors during power-on of the integrated circuit.

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    The document describes the power-up sequence from G3 state to S0 state for the C51/MCP51 microcontroller. It shows that the various power planes and clocks are enabled in a specific sequence to ensure proper powering and initialization of the device. First, the reset and crystal clock signals are activated along with the primary power supplies. Then each subsequent block such as the CPU, PLLs, and peripheral power planes are enabled only after the previous block is stable. This staged powering approach helps avoid faults or errors during power-on of the integrated circuit.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    37 views1 page

    Sequence v31.8

    Uploaded by

    Ashok Jangra
    The document describes the power-up sequence from G3 state to S0 state for the C51/MCP51 microcontroller. It shows that the various power planes and clocks are enabled in a specific sequence to ensure proper powering and initialization of the device. First, the reset and crystal clock signals are activated along with the primary power supplies. Then each subsequent block such as the CPU, PLLs, and peripheral power planes are enabled only after the previous block is stable. This staged powering approach helps avoid faults or errors during power-on of the integrated circuit.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
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    Power Sequencing

    5.4.3.

    G3-to-S0 Power-Up Sequence


    Figure 5-3 shows the C51/MCP51 G3-to-S0 Power-up Sequence diagram. This sequence is followed by the Cold Reset Sequence in Chapter 6 (see Figure 6-2).
    P S 122

    LP C_ P D# P S 121 HT _ V L D P S 115 +1 .2 V _ HT P S 1 16

    H T V DD _E N

    P S 1 14

    CP U_V LD P S 112 +V _ C P U P S 1 13

    CP UV DD _E N

    P S 111

    C LK OU T _ 2 0 0 MHZ L P C _ CL K

    P S 1 10

    Running Running

    S US C LK (32 kH z)

    P W R GD P S 108 C ORE P o w e rP l a n e s

    P S 109

    S LP _S 3 # P S 106

    P S 107

    P S 120 ME M_ V L D P S 105 +2 .5 V _ S U S +1 .25 V _V T T _ S U S S LP _S 5 # P S 104

    P W R GD _ S B P S 1 01 2 5 Mh z xta l B U F_ 25 MH Z +5 V _ D UA L +3 .3 V _ D UA L +1 .5 V _ D UA L

    P S 102

    Running
    P S 100

    +3.0 V _ V B A T

    CO RE P ow e r P la ne s inc lude :

    +1 .2 V Co re , +1 .5 V _ P L L _H T , +3.3 V _ P LL _ HT , +1 .2 V _ P E _ P L L _ A V D D, +1.2 V _ P E _P L L_ DV D D, +1 .2V _ P E _ P L L _ C OR E , +1 .2 V _ P E _ D, +1 .2 V _ P E _ A , +3 .3 V _ P E _ P L L _ CORE , +1 .5 V _ S P _ P L L _ A V D D, +1.5 V _ S P _P L L_ DV D D, +1 .5V _ S P _ P L L _ C OR E ,, +1 .5 V _ S P _ D, +1 .5 V _ S P _ A , +3 .3 V _ S P _ P L L _ CORE , +3 .3 V _ P L L _C P U, +3 .3V _ S P _ P L L _ U S B , +3 .3 V , +5V

    P ow e r P la ne s a re in Re d M CP 5 1 output s igna ls a re in Blue M othe rboa rd ge ne ra te d inputs to M C P 5 1 a re in P urple

    Figure 5-3. C51/MCP51 Power-Up Sequence

    DG-01632-001_v3.8 10/27/05

    112

    NVIDIA CONFIDENTIAL

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