CONTENTS

Organizational Profile
Design
Manufacturing
2.1 PCB CAM
2.2 Panelization
2.3 Copper patterning
2.3.1 Subtractive, aitive an se!i"aitive
processes
2.3.2 Patterning !et#o b$ volu!e
2.3.2.1 %arge volu!e
2.3.2.2 S!all volu!e
2.3.2.3 &obb$ist
2.3.3 C#e!ical etc#ing
2.' (nner la$er auto!ate optical inspection )AO(*
2.+ %a!ination
2., Drilling
2.- Plating an coating
2.. Soler resist application
2./ %egen printing
2.10 Bare"boar test
2.11 Asse!bl$
2.12 Protection an pac1aging
3 PCB c#aracteristics
3.1 2#roug#"#ole tec#nolog$
3.2 Surface"!ount tec#nolog$
1
3.3 Circuit properties of t#e PCB
3.' Materials
3.'.1 %a!inates
3.'.2 Copper t#ic1ness
3.'.3 Safet$ certification )3S*
Multi4ire boars
+ Cor4oo construction
, &istor$
Bibliograp#$
DESIGN AND DEVELOPMENT OF AT89S51 BASED PSO TUNED
PID TEMPRETURE CONTROLLER
A Dissertation Sub!itte in Partial 5ulfil!ent of t#e 6e7uire!ents
5or t#e A4ar of Degree of
Master of Science
In
Electronic Science
Sub!itte b$
1
Prashant Kumar Sharma
3ner t#e 8uiance of9
Dr. T.K. Saxena
C#ief Scientist an &ea
Acoustic, 3ltrasonic : ;ibration Stanars
an <lectronics an (nstru!entation Cell
CS(6"=ational P#$sical %aborator$
Dr. >. S. >ris#nan 6oa
=e4 Del#i" 110 012
Department of Electronic Science
Kurukshetra Uniersit!" Kurukshetra #ar!ana
?ul$ 2013
DEC$%&%TION
( Prashant Kumar Sharma, stuent of M.Sc. Electronic Science
IV Sem #ereb$ eclare t#at t#e pro@ect title ADesign and
Development of AT8S!" #ased PS$ Tuned PID Temperature
%ontrollerB 4#ic# is sub!itte b$ !e to Depart!ent of
<lectronic Science, Kuru&shetra 'niversit() Kuru&shetra
*ar(ana in partial fulfill!ent of re7uire!ent for t#e a4ar of t#e
egree of Master of Science in <lectronic Science, #as not been
previousl$ for!e t#e basis for t#e a4ar of an$ egree, iplo!a
or ot#er si!ilar title or recognition.
Date Pras#ant >u!ar S#ar!a
M.Sc. <lectronic Science
>uru1s#etra 3niversit$,>uru1s#etra
1
%CKNO'$ED(EMENTS
Apart fro! t#e efforts of !e, t#e success of an$ pro@ect epens largel$ on
t#e encourage!ent an guielines of !an$ ot#ers.
( ta1e t#is opportunit$ to eCpress !$ gratitue to t#e people 4#o #ave been
instru!ental in t#e successful co!pletion of t#is pro@ect. ( 4oul li1e to
s#o4 !$ greatest appreciation to Dr. T. K. Sa+ena, %hief Scientist and
*ead) Acoustics) 'ltrasonic , Vi-rations Standards and Electronics ,
Instrumentation %ell) %SI./0ational Ph(sical 1a-orator( 20P13) 0e4
Delhi. &is vast eCperience an eep uner" staning of t#e sub@ect prove
to be i!!ense #elp to !e, an also #is profoun vie4 points an
eCtraorinar$ !otivation enlig#tene !e in !an$ 4a$s. ( canDt sa$ t#an1
$ou enoug# for #is tre!enous support an #elp. Eit#out #is
encourage!ent an guiance t#is pro@ect 4oul not #ave !aterialize.
( also o4e !$ gratitue to Mr. Avneesh Mittal) Mrs. Pri(an&a 5ain) and
Mrs. Poonam Sethi #ist, for t#eir co"operation, constructive criticis!,
valuable guiance an constant encourage!ent.
( a! also t#an1ful to 4#ole Department of Electronic Science)
Kuru&shetra 'niversit() Kuru&shetra *ar(ana for proviing all t#e co"
operation an support for t#e pro@ect.
%ast but not least ( 4oul li1e to s#o4 !$ gratitue to !$ parents an !$
friens 4#ose support is greatl$ value.
1
Printe) circuit *oar)
A printe circuit boar )PCB* !ec#anicall$ supports an electricall$
connects electronic co!ponents using conuctive trac1s, pas an ot#er
features etc#e fro! copper s#eets la!inate onto a non"conuctive substrate. PCBs
can be single sie )one copper la$er*, ouble sie )t4o copper la$ers* or !ulti"la$er.
Conuctors on ifferent la$ers are connecte 4it# plate"t#roug# #oles calle vias.
Avance PCBs !a$ contain co!ponents " capacitors, resistors or active evices "
e!bee in t#e substrate.
Printe circuit boars are use in all but t#e si!plest electronic proucts. Alternatives
to PCBs inclue 4ire 4rap an point"to"point construction. PCBs re7uire t#e aitional
esign effort to la$ out t#e circuit but !anufacturing an asse!bl$ can be auto!ate.
Manufacturing circuits 4it# PCBs is c#eaper an faster t#an 4it# ot#er 4iring !et#os
as co!ponents are !ounte an 4ire 4it# one single part. 5urt#er!ore, operator
4iring errors are eli!inate.
E#en t#e boar #as onl$ copper connections an no e!bee co!ponents it is !ore
correctl$ calle a printe 4iring boar )PEB* or etc#e 4iring boar. Alt#oug# !ore
accurate, t#e ter! printe 4iring boar #as fallen into isuse. A PCB populate 4it#
electronic co!ponents is calle a printe circuit asse!bl$ )PCA*, printe circuit boar
asse!bl$ or PCB asse!bl$ )PCBA*. 2#e (PC preferre ter! for asse!ble boars
is circuit car asse!bl$ )CCA*, for asse!ble bac1planes it is bac1plane asse!blies.
2#e ter! PCB is use infor!all$ bot# for bare an asse!ble boars.
2#e 4orl !ar1et for bare PCBs reac#e nearl$ F,0 billion in 2012
1
#istor!
Develop!ent of t#e !et#os use in !oern printe circuit boars starte earl$ in t#e
20t# centur$. (n 1/03, a 8er!an inventor, Albert &anson, escribe flat foil conuctors
la!inate to an insulating boar, in !ultiple la$ers. 2#o!as <ison eCperi!ente 4it#
c#e!ical !et#os of plating conuctors onto linen paper in 1/0'. Art#ur Berr$ in 1/13
patente a print"an"etc# !et#o in Britain, an in t#e 3nite States MaC Sc#oop
obtaine a patent to fla!e"spra$ !etal onto a boar t#roug# a patterne !as1. C#arles
Durcase in 1/2- patente a !et#o of electroplating circuit patterns.
2#e Austrian engineer Paul <isler invente t#e printe circuit 4#ile 4or1ing in <nglan
aroun 1/3, as part of a raio set. Aroun 1/'3 t#e 3SA began to use t#e tec#nolog$
on a large scale to !a1e proCi!it$ fuses for use in Eorl Ear ((. After t#e 4ar, in 1/'.,
t#e 3SA release t#e invention for co!!ercial use. Printe circuits i not beco!e
co!!onplace in consu!er electronics until t#e !i"1/+0s, after t#e Auto"
Se!bl$ process 4as evelope b$ t#e 3nite States Ar!$. At aroun t#e sa!e ti!e in
Britain 4or1 along si!ilar lines 4as carrie out b$ 8eoffre$ Du!!er, t#en at
t#e 66D<.
A PCB as a design on a computer (left) and realized as a board assembly populated with components
(right). The board is double sided, with throughhole plating, green solder resist and a white legend.
Both surface mount and throughhole components ha!e been used.
1
A PCB in a computer mouse. The component side (left) and the printed side (right).
The component side of a PCB in a computer mouse" some e#amples for common components and
their reference designations in the legend.
Component and solderside
1
Before printe circuits )an for a 4#ile after t#eir invention*, point"to"point
construction 4as use. 5or protot$pes, or s!all prouction runs, 4ire 4rap or turret
boar can be !ore efficient. Preating t#e printe circuit invention, an si!ilar in
spirit, 4as ?o#n SargroveGs 1/3,H1/'- <lectronic Circuit Ma1ing <7uip!ent )<CM<*
4#ic# spra$e !etal onto a Ba1elite plastic boar. 2#e <CM< coul prouce 3 raios
per !inute.
During Eorl Ear ((, t#e evelop!ent of t#e anti"aircraft proCi!it$ fuse re7uire an
electronic circuit t#at coul 4it#stan being fire fro! a gun, an coul be prouce in
7uantit$. 2#e Centralab Division of 8lobe 3nion sub!itte a proposal 4#ic# !et t#e
re7uire!ents9 a cera!ic plate 4oul be screenprinte 4it# !etallic paint for conuctors
an carbon !aterial for resistors, 4it# cera!ic isc capacitors an sub!iniature
vacuu! tubes solere in place. 2#e tec#ni7ue prove viable, an t#e resulting patent
on t#e process, 4#ic# 4as classifie b$ t#e 3.S. Ar!$, 4as assigne to 8lobe 3nion. (t
4as not until 1/.' t#at t#e (nstitute of <lectrical an <lectronics <ngineers )(<<<*
a4are Mr. &arr$ E. 6ubinstein, t#e for!er #ea of 8lobe 3nionGs Centralab
Division, its covete Cleo Brunetti A4ar for earl$ 1e$ contributions to t#e
evelop!ent of printe co!ponents an conuctors on a co!!on insulating
substrate. As 4ell, Mr. 6ubinstein 4as #onore in 1/.' b$ #is al!a !ater, t#e
3niversit$ of Eisconsin"Maison, for #is innovations in t#e tec#nolog$ of printe
electronic circuits an t#e fabrication of capacitors.
Originall$, ever$ electronic co!ponent #a 4ire leas, an t#e PCB #a #oles rille
for eac# 4ire of eac# co!ponent. 2#e co!ponentsG leas 4ere t#en passe t#roug# t#e
#oles an solere to t#e PCB trace. 2#is !et#o of asse!bl$ is calle t#roug#"
#ole construction. (n 1/'/, Moe Abra!son an Stanislaus 5. Dan1o of t#e 3nite States
Ar!$ Signal Corps evelope t#e Auto"Se!bl$ process in 4#ic# co!ponent leas
4ere inserte into a copper foil interconnection pattern an ip solere. 2#e patent
t#e$ obtaine in 1/+, 4as assigne to t#e 3.S. Ar!$. Eit# t#e evelop!ent of boar
la!ination an etc#ing tec#ni7ues, t#is concept evolve into t#e stanar printe circuit
boar fabrication process in use toa$. Solering coul be one auto!aticall$ b$
passing t#e boar over a ripple, or 4ave, of !olten soler in a 4ave"solering !ac#ine.
&o4ever, t#e 4ires an #oles are 4asteful since rilling #oles is eCpensive an t#e
protruing 4ires are !erel$ cut off.
1
5ro! t#e 1/.0s s!all surface !ount parts #ave been use increasingl$ instea of
t#roug#"#ole co!ponentsI t#is #as le to s!aller boars for a given functionalit$ an
lo4er prouction costs, but 4it# so!e aitional ifficult$ in servicing fault$ boars.
&istoricall$ !an$ !easure!ents relate to PCB esign 4ere specifie in !ultiples of
a t#ousant# of an inc#, often calle J!ilsJ. 5or eCa!ple, D(P an !ost ot#er t#roug#"
#ole co!ponents #ave pins locate on a gri spacing of 100 !ils, in orer to
be breaboar"frienl$. Surface"!ount SO(C co!ponents #ave a pin pitc# of +0
!ils. SOP co!ponents #ave a pin pitc# of 2+ !ils. %evel B tec#nolog$ reco!!ens a
!ini!u! trace 4it# of . !ils, 4#ic# allo4s Jouble"trac1J H t4o traces bet4een D(P
pins.
Desi+n
A board designed in $%&'" the sweeping cur!es in the traces are e!idence of freehand
design using selfadhesi!e tape.
Printe circuit boar art4or1 generation 4as initiall$ a full$ !anual process one on
clear !$lar s#eets at a scale of usuall$ 2 or ' ti!es t#e esire size. 2#e sc#e!atic
iagra! 4as first converte into a la$out of co!ponents pin pas, t#en traces 4ere
route to provie t#e re7uire interconnections. Pre"printe non"reproucing !$lar
gris assiste in la$out, an rub"on r$ transfers of co!!on arrange!ents of circuit
ele!ents )pas, contact fingers, integrate circuit profiles, an so on* #elpe
1
stanarize t#e la$out. 2races bet4een evices 4ere !ae 4it# self"a#esive tape. 2#e
finis#e la$out Jart4or1J 4as t#en p#otograp#icall$ reprouce on t#e resist la$ers of
t#e blan1 coate copper"cla boars.
Moern practice is less labor"intensive since co!puters can auto!aticall$ perfor!
!an$ of t#e la$out steps. 2#e general progression for a co!!ercial printe circuit
boar esign 4oul inclue9
,- Schematic capture throu+h an electronic )esi+n
automation tool.
Car i!ensions an te!plate are ecie base on re7uire circuitr$ an case of t#e
PCB. Deter!ine t#e fiCe co!ponents an #eat if re7uire.
Deciing stac1 la$ers of t#e PCB. 1 to 12 la$ers or !ore epening on esign
co!pleCit$. Ground plane an power plane are ecie. Signal planes 4#ere
signals are route are in top la$er as 4ell as internal la$ers.
Line impedance eter!ination using ielectric la$er t#ic1ness, routing copper
t#ic1ness an trace"4it#. 2race separation also ta1en into account in case of
ifferential signals. Microstrip, stripline or ual stripline can be use to route signals.
Place!ent of t#e co!ponents. 2#er!al consierations an geo!etr$ are ta1en into
account. Vias an lans are !ar1e.
6outing t#e signal traces. 5or opti!al EMI perfor!ance #ig# fre7uenc$ signals are
route in internal la$ers bet4een po4er or groun planes as power planes be#ave as
groun for AC.
.- (er*er file +eneration for manufacturin+.
(n t#e esign of t#e PCB art4or1, a po4er plane is t#e counterpart to t#e groun
plane an be#aves as an AC signal groun, 4#ile proviing DC voltage for po4ering
circuits !ounte on t#e PCB. (n electronic esign auto!ation )<DA* esign tools,
po4er planes )an groun planes* are usuall$ ra4n auto!aticall$ as a negative la$er,
4it# clearances or connections to t#e plane create auto!aticall$.
1
Manufacturin+
PCB !anufacturing consists of !an$ steps.
,- PC/ C%M
Manufacturers never use t#e 8erber or <Ccellon files irectl$ on t#eir e7uip!ent, but
al4a$s rea t#e! into t#eir CAM s$ste!. PCBs cannot be !anufacture professionall$
4it#out a CAM s$ste!. 2#e PCB CAM s$ste! perfor!s t#e follo4ing functions9
(nput of t#e 8erber ata
;erif$ t#e ataI optionall$ D5M
Co!pensate for eviations in t#e !anufacturing processes )e.g. scaling to co!pensate
for istortions uring la!ination*
Panelize
Output of t#e igital tools )la$er i!ages, rill files, AO( ata, electrical test files,.*
.- Paneli0ation
Panelization is a proceure use to #anle PCBs 4#ic# 4oul ot#er4ise be too s!all to
process. A nu!ber of ientical circuits are printe onto a larger boar )t#e panel* 4#ic#
can t#en be #anle in t#e nor!al 4a$. 2#e panel is bro1en apart into iniviual PCBs
4#en all ot#er processing is co!plete. Separating t#e iniviual PCBs is fre7uentl$
aie b$ rilling or routing perforations along t#e bounaries of t#e iniviual circuits,
!uc# li1e a s#eet of postage sta!ps. Anot#er !et#o, 4#ic# ta1es less space, is to cut
;"s#ape grooves across t#e full i!ension of t#e panel. 2#e iniviual PCBs can t#en
be bro1en apart along t#is line of 4ea1ness.
2#e process of re!oving iniviual PCBs fro! a larger boar is calle Depaneling.
E#ile rilleKroute perforations an grooves 4ere co!!on for a nu!ber of $ears,
toa$ t#is is often one b$ lasers, 4#ic# cut t#e boar 4it# no contact. 2#is reuces t#e
1
stresses on t#e fragile circuits cause b$ tor7ue. 2#is !et#o is often co!pletel$
auto!ate 4it# full boars entering t#e laser epaneling !ac#ine via conve$or, being
cut into iniviual pieces b$ laser, an leaving t#e s$ste! via conve$or, an so!eti!es
stac1e, on t#e ot#er sie.
1- Copper Patternin+
2#e pattern in t#e !anufacturerGs PCB CAM s$ste! is usuall$ output on a p#oto!as1
)p#oto"tool, fil!* b$ a p#otoplotter an replicate via sil1 screen printing or b$
eCposing on a p#oto"sensitive p#otoresist coating. Direct i!aging tec#ni7ues are
so!eti!es use for #ig#"resolution re7uire!ents.
o Su*tractie" a))itie an) semi2a))itie processes
1
The two processing methods used to produce a doublesided P(B with plated through
holes.
Subtractive !et#os re!ove copper fro! an entirel$ copper"coate boar to leave onl$
t#e esire copper pattern9
Silk screen printing uses etc#"resistant in1s to protect t#e copper foil. Subse7uent
etc#ing re!oves t#e un4ante copper. Alternativel$, t#e in1 !a$ be conuctive, printe
on a blan1 )non"conuctive* boar. 2#e latter tec#ni7ue is also use in t#e !anufacture
of hybrid circuits.
Photoengraving uses a p#oto!as1 an eveloper to selectivel$ re!ove a p#otoresist
coating. 2#e re!aining p#otoresist protects t#e copper foil. Subse7uent etc#ing
re!oves t#e un4ante copper.
P! milling uses a t4o or t#ree"aCis !ec#anical !illing s$ste! to !ill a4a$ t#e
copper foil fro! t#e substrate. A PCB !illing !ac#ine )referre to as a GPCB
Protot$perG* operates in a si!ilar 4a$ to a plotter, receiving co!!ans fro! t#e #ost
soft4are t#at control t#e position of t#e !illing #ea in t#e C, $, an )if relevant* z aCis.
Data to rive t#e Protot$pe is eCtracte fro! files generate in PCB esign soft4are
an store in "PGL or Gerber #le for!at.
(n aitive !et#os t#e pattern is electroplate onto a bare substrate using a co!pleC
process. 2#e avantage of t#e aitive !et#o is t#at less !aterial is neee an less
4aste is prouce. (n t#e full aitive process t#e bare la!inate is covere 4it# a
p#otosensitive fil! 4#ic# is i!age )eCpose to lig#t t#roug# a !as1 an t#en
evelope 4#ic# re!oves t#e uneCpose fil!*. 2#e eCpose areas are sensitize in a
c#e!ical bat#, usuall$ containing pallaiu! an si!ilar to t#at use for t#roug# #ole
plating 4#ic# !a1es t#e eCpose area capable of boning !etal ions. 2#e la!inate is
t#en plate 4it# copper in t#e sensitize areas. E#en t#e !as1 is strippe, t#e PCB is
finis#e.
Se!i"aitive is t#e !ost co!!on process9 2#e unpattern boar #as a t#in la$er of
copper alrea$ on it. A reverse !as1 is t#en applie. )3nli1e a subtractive process
1
!as1, t#is !as1 eCposes t#ose parts of t#e substrate t#at 4ill eventuall$ beco!e t#e
traces.* Aitional copper is t#en plate onto t#e boar in t#e un!as1e areasI copper
!a$ be plate to an$ esire 4eig#t. 2in"lea or ot#er surface platings are t#en applie.
2#e !as1 is strippe a4a$ an a brief etc#ing step re!oves t#e no4"eCpose bare
original copper la!inate fro! t#e boar, isolating t#e iniviual traces. So!e single"
sie boars 4#ic# #ave plate"t#roug# #oles are !ae in t#is 4a$. 8eneral
<lectric !ae consu!er raio sets in t#e late 1/,0s using aitive boars.
2#e )se!i"*aitive process is co!!onl$ use for !ulti"la$er boars as it facilitates
t#e plating"t#roug# of t#e #oles to prouce conuctive vias in t#e circuit boar.
PCB copper electroplating line in the process of
pattern plating copper.
PCBs in process of ha!ing copper pattern plated,
notice the blue dry film resist.
o Patternin+ metho) *! olume
2#e !et#o c#osen epens on t#e nu!ber of boars to be prouce.
$ar+e olume
Silk screen printingHt#e !ain co!!ercial !et#o.
P#otograp#ic !et#osHuse 4#en fine line 4it#s are re7uire.
Small olume
Print onto transparent fil! an use as p#oto!as1 along 4it# p#oto"sensitize boars.
)i.e., pre"sensitize boars*, t#en etc#. )Alternativel$, use a fil! p#oto plotter*.
%aser resist ablation9 Spra$ blac1 paint onto copper cla la!inate, place into $ laser
plotter. 2#e laser raster"scans t#e PCB an ablates )vaporizes* t#e paint 4#ere no resist
1
is 4ante. <tc#. )=ote9 laser copper ablation is rarel$ use an is consiere
eCperi!ental.
3se a C=C"!ill 4it# a spae"s#ape )i.e., a flat"ene cone* cutter or !iniature en"
!ill to rout a4a$ t#e unesire copper, leaving onl$ t#e traces.
#o**!ist
%aser"printe resist9 %aser"print onto transparenc$ fil!, #eat"transfer 4it# an iron or
!oifie la!inator onto bare la!inate, touc# up 4it# a !ar1er, t#en etc#.
;in$l fil! an resist, non"4as#able !ar1er, so!e ot#er !et#os. %abor"intensive, onl$
suitable for single boars
o Chemical etchin+
C#e!ical etc#ing is usuall$ one 4it# a!!oniu! persulfate or ferric c#lorie. 5or
P2& )plate"t#roug# #oles*, aitional steps of electroless eposition are one after t#e
#oles are rille, t#en copper is electroplate to buil up t#e t#ic1ness, t#e boars are
screene, an plate 4it# tinKlea. 2#e tinKlea beco!es t#e resist leaving t#e bare
copper to be etc#e a4a$.
2#e si!plest !et#o, use for s!all"scale prouction an often b$ #obb$ists, is
i!!ersion etc#ing, in 4#ic# t#e boar is sub!erge in etc#ing solution suc# as ferric
c#lorie. Co!pare 4it# !et#os use for !ass prouction, t#e etc#ing ti!e is long.
&eat an agitation can be applie to t#e bat# to spee t#e etc#ing rate. (n bubble
etc#ing, air is passe t#roug# t#e etc#ant bat# to agitate t#e solution an spee up
etc#ing. Splas# etc#ing uses a !otor"riven pale to splas# boars 4it# etc#antI t#e
process #as beco!e co!!erciall$ obsolete since it is not as fast as spra$ etc#ing. (n
spra$ etc#ing, t#e etc#ant solution is istribute over t#e boars b$ nozzles, an
recirculate b$ pu!ps. A@ust!ent of t#e nozzle pattern, flo4 rate, te!perature, an
etc#ant co!position gives preictable control of etc#ing rates an #ig# prouction
rates.
As !ore copper is consu!e fro! t#e boars, t#e etc#ant beco!es saturate an less
effectiveI ifferent etc#ants #ave ifferent capacities for copper, 4it# so!e as #ig# as
1+0 gra!s of copper per litre of solution. (n co!!ercial use, etc#ants can be
regenerate to restore t#eir activit$, an t#e issolve copper recovere an sol.
1
S!all"scale etc#ing re7uires attention to isposal of use etc#ant, 4#ic# is corrosive
an toCic ue to its !etal content.
2#e etc#ant re!oves copper on all surfaces eCpose b$ t#e resist. J3nercutJ occurs
4#en etc#ant attac1s t#e t#in ege of copper uner t#e resistI t#is can reuce conuctor
4it#s an cause open"circuits. Careful control of etc# ti!e is re7uire to prevent
unercut. E#ere !etallic plating is use as a resist, it can Jover#angJ 4#ic# can cause
s#ort"circuits bet4een a@acent traces 4#en closel$ space. Over#ang can be re!ove
b$ 4ire"brus#ing t#e boar after etc#ing.
3- Inner la!er automate) optical inspection 4%OI-
2#e inner la$ers are given a co!plete !ac#ine inspection before la!ination because
after4ars !ista1es cannot be correcte. 2#e auto!atic optical inspection s$ste! scans
t#e boar an co!pares it 4it# t#e igital i!age generate fro! t#e original esign
ata.
5- $amination
Multi"la$er printe circuit boars #ave trace la$ers insie t#e boar. One 4a$ to !a1e a
'"la$er PCB is to use a t4o"sie copper"cla la!inate, etc# t#e circuitr$ on bot# sies,
t#en la!inate to t#e top an botto! prepare an copper foil. %a!ination is one b$
placing t#e stac1 of !aterials in a press an appl$ing pressure an #eat for a perio of
ti!e. 2#is results in an inseparable one piece prouct. (t is t#en rille, plate, an
etc#e again to get traces on top an botto! la$ers. 5inall$ t#e PCB is covere 4it#
soler !as1, !ar1ing legen, an a surface finis# !a$ be applie. Multi"la$er PCBs
allo4 for !uc# #ig#er co!ponent ensit$.
6- Drillin+
1
)ollow ri!ets.
&oles t#roug# a PCB are t$picall$ rille 4it# s!all"ia!eter rill bits !ae of soli
coate tungsten carbie. Coate tungsten carbie is reco!!ene since !an$ boar
!aterials are ver$ abrasive an rilling !ust be #ig# 6PM an #ig# fee to be cost
effective. Drill bits !ust also re!ain s#arp so as not to !ar or tear t#e traces. Drilling
4it# #ig#"spee"steel is si!pl$ not feasible since t#e rill bits 4ill ull 7uic1l$ an t#us
tear t#e copper an ruin t#e boars. 2#e rilling is perfor!e b$ auto!ate rilling
!ac#ines 4it# place!ent controlle b$ a rill tape or rill file. 2#ese co!puter"
generate files are also calle nu!ericall$ controlle rill )=CD* files or J<Ccellon
filesJ. 2#e rill file escribes t#e location an size of eac# rille #ole. 2#ese #oles are
often fille 4it# annular rings )#ollo4 rivets* to create vias. ;ias allo4 t#e electrical
an t#er!al connection of conuctors on opposite sies of t#e PCB.
E#en ver$ s!all vias are re7uire, rilling 4it# !ec#anical bits is costl$ because of
#ig# rates of 4ear an brea1age. (n t#is case, t#e vias !a$ be evaporate b$ lasers.
%aser"rille vias t$picall$ #ave an inferior surface finis# insie t#e #ole. 2#ese #oles
are calle !icro vias.
(t is also possible 4it# controlle"ept# rilling, laser rilling, or b$ pre"rilling t#e
iniviual s#eets of t#e PCB before la!ination, to prouce #oles t#at connect onl$
so!e of t#e copper la$ers, rat#er t#an passing t#roug# t#e entire boar. 2#ese #oles are
calle blin vias 4#en t#e$ connect an internal copper la$er to an outer la$er, or burie
vias 4#en t#e$ connect t4o or !ore internal copper la$ers an no outer la$ers.
2#e #ole 4alls for boars 4it# 2 or !ore la$ers can be !ae conuctive an t#en
electroplate 4it# copper to for! plate"t#roug# #oles. 2#ese #oles electricall$
connect t#e conucting la$ers of t#e PCB. 5or !ultila$er boars, t#ose 4it# 3 la$ers or
!ore, rilling t$picall$ prouces a s!ear of t#e #ig# te!perature eco!position
proucts of boning agent in t#e la!inate s$ste!. Before t#e #oles can be plate
t#roug#, t#is s!ear !ust be re!ove b$ a c#e!ical e"s!ear process, or b$ plas!a"
etc#. 2#e e"s!ear process ensures t#at a goo connection is !ae to t#e copper la$ers
4#en t#e #ole is plate t#roug#. On #ig# reliabilit$ boars a process calle etc#"bac1 is
perfor!e c#e!icall$ 4it# a potassiu! per!anganate base etc#ant or plas!a. 2#e
1
etc#"bac1 re!oves resin an t#e glass fibers so t#at t#e copper la$ers eCten into t#e
#ole an as t#e #ole is plate beco!e integral 4it# t#e eposite copper.
7- Platin+ an) coatin+
PCBs are plate 4it# soler, tin, or gol over nic1el as a resist for etc#ing a4a$ t#e
unneee unerl$ing copper.
After PCBs are etc#e an t#en rinse 4it# 4ater, t#e soler !as1 is applie, an t#en
an$ eCpose copper is coate 4it# soler, nic1elKgol, or so!e ot#er anti"corrosion
coating.
Matte soler is usuall$ fuse to provie a better boning surface or strippe to bare
copper. 2reat!ents, suc# as benzi!iazolet#iol, prevent surface oCiation of bare
copper. 2#e places to 4#ic# co!ponents 4ill be !ounte are t$picall$ plate, because
untreate bare copper oCiizes 7uic1l$, an t#erefore is not reail$ soler able.
2raitionall$, an$ eCpose copper 4as coate 4it# soler b$ #ot air soler leveling
)&AS%*. 2#e &AS% finis# prevents oCiation fro! t#e unerl$ing copper, t#ereb$
guaranteeing a soler able surface. 2#is soler 4as a tin"lea allo$, #o4ever ne4 soler
co!pouns are no4 use to ac#ieve co!pliance 4it# t#e 6o&S irective in t#e <3 an
3S, 4#ic# restricts t#e use of lea. One of t#ese lea"free co!pouns is S=100C%,
!ae up of //.3L tin, 0.-L copper, 0.0+L nic1el, an a no!inal of ,0pp!
ger!aniu!.
(t is i!portant to use soler co!patible 4it# bot# t#e PCB an t#e parts use. An
eCa!ple is Ball 8ri Arra$ )B8A* using tin"lea soler balls for connections losing
t#eir balls on bare copper traces or using lea"free soler paste.
Ot#er plantings use are OSP )organic surface protectant*, i!!ersion silver )(Ag*,
i!!ersion tin, electroless nic1el 4it# i!!ersion gol coating )<=(8*, electroless
nic1el electroless pallaiu! i!!ersion gol )<=<P(8* an irect gol plating )over
nic1el*. <ge connectors, place along one ege of so!e boars, are often nic1el plate
t#en gol plate. Anot#er coating consieration is rapi iffusion of coating !etal into
2in soler. 2in for!s inter!etallic suc# as Cu+Sn, an Ag3Cu t#at issolve into t#e
2in li7uis or solius )M+0C*, stripping surface coating or leaving vois.
1
<lectroc#e!ical !igration )<CM* is t#e gro4t# of conuctive !etal fila!ents on or in
a printe circuit boar )PCB* uner t#e influence of a DC voltage bias. Silver, zinc, an
alu!inu! are 1no4n to gro4 4#is1ers uner t#e influence of an electric fiel. Silver
also gro4s conucting surface pat#s in t#e presence of #alie an ot#er ions, !a1ing it
a poor c#oice for electronics use. 2in 4ill gro4 J4#is1ersJ ue to tension in t#e plate
surface. 2in"%ea or Soler plating also gro4s 4#is1ers, onl$ reuce b$ t#e
percentage 2in replace. 6eflo4 to !elt soler or tin plate to relieve surface stress
lo4ers 4#is1er incience. Anot#er coating issue is tin pest, t#e transfor!ation of tin to
a po4er$ allotrope at lo4 te!perature.
8- Sol)er resist application
Areas t#at s#oul not be solere !a$ be covere 4it# soler resist )soler !as1*. One
of t#e !ost co!!on soler resists use toa$ is calle %P( )li7ui p#otoi!ageable*. A
p#oto sensitive coating is applie to t#e surface of t#e PEB, t#en eCpose to lig#t
t#roug# t#e soler !as1 i!age fil!, an finall$ evelope 4#ere t#e uneCpose areas
are 4as#e a4a$. Dr$ fil! soler !as1 is si!ilar to t#e r$ fil! use to i!age t#e
PEB for plating or etc#ing. After being la!inate to t#e PEB surface it is i!age an
evelop as %P(. Once co!!on but no longer co!!onl$ use because of its lo4
accurac$ an resolution is to screen print epoC$ in1. Soler resist also provies
protection fro! t#e environ!ent
.
9- $e+en) printin+
A legen is often printe on one or bot# sies of t#e PCB. (t contains t#e co!ponent
esignators, s4itc# settings, test points an ot#er inications #elpful in asse!bling,
testing an servicing t#e circuit boar.
2#ere are t#ree !et#os to print t#e legen.
Silk screen printing epoC$ in1 4as t#e establis#e !et#o. (t 4as so co!!on t#at
legen is often !isna!e sil1 or sil1screen.
%i7ui p#oto i!aging is a !ore accurate !et#o t#an screen printing.
(n1 @et printing is ne4 but increasingl$ use. (n1 @et can print variable ata suc# as a
teCt or bar code 4it# a serial number.
,:- /are2*oar) test
1
3npopulate boars !a$ be sub@ecte to a bare"boar test 4#ere eac# circuit
connection )as efine in a netlist* is verifie as correct on t#e finis#e boar. 5or #ig#"
volu!e prouction, a be of nails tester, a fiCture or a rigi neele aapter is use to
!a1e contact 4it# copper lans or #oles on one or bot# sies of t#e boar to facilitate
testing. A co!puter 4ill instruct t#e electrical test unit to appl$ a s!all voltage to eac#
contact point on t#e be"of"nails as re7uire, an verif$ t#at suc# voltage appears at
ot#er appropriate contact points. A Js#ortJ on a boar 4oul be a connection 4#ere
t#ere s#oul not be oneI an JopenJ is bet4een t4o points t#at s#oul be connecte but
are not. 5or s!all" or !eiu!"volu!e boars, fl$ing probe an fl$ing"gri testers use
!oving test #eas to !a1e contact 4it# t#e copperKsilverKgolKsoler lans or #oles to
verif$ t#e electrical connectivit$ of t#e boar uner test. Anot#er !et#o for testing
is inustrial C2 scanning, 4#ic# can generate a 3D renering of t#e boar along 4it#
2D i!age slices an can s#o4 etails suc# as solere pat#s an connections.
,,- %ssem*l!
PCB with test connection pads
After t#e printe circuit boar )PCB* is co!plete, electronic co!ponents !ust be
attac#e to for! a functional printe circuit asse!bl$, or PCA )so!eti!es calle a
Jprinte circuit boar asse!bl$J PCBA*. (n t#roug#"#ole construction, co!ponent
leas are inserte in #oles. (n surface"!ount )SM2 " surface !ount tec#nolog$*
construction, t#e co!ponents are place on pas or lans on t#e outer surfaces of t#e
1
PCB. (n bot# 1ins of construction, co!ponent leas are electricall$ an !ec#anicall$
fiCe to t#e boar 4it# a !olten !etal soler.
2#ere are a variet$ of solering tec#ni7ues use to attac# co!ponents to a PCB. &ig#
volu!e prouction is usuall$ one 4it# SM2 place!ent !ac#ine an bul1 4ave
solering or reflo4 ovens, but s1ille tec#nicians are able to soler ver$ tin$ parts )for
instance 0201 pac1ages 4#ic# are 0.02 in. b$ 0.01 in.* b$ #an uner a !icroscope,
using t4eezers an a fine tip solering iron for s!all volu!e protot$pes. So!e parts
!a$ be eCtre!el$ ifficult to soler b$ #an, suc# as B8A pac1ages.
Often, t#roug#"#ole an surface"!ount construction !ust be co!bine in a single
asse!bl$ because so!e re7uire co!ponents are available onl$ in surface"!ount
pac1ages, 4#ile ot#ers are available onl$ in t#roug#"#ole pac1ages. Anot#er reason to
use bot# !et#os is t#at t#roug#"#ole !ounting can provie neee strengt# for
co!ponents li1el$ to enure p#$sical stress, 4#ile co!ponents t#at are eCpecte to go
untouc#e 4ill ta1e up less space using surface"!ount tec#ni7ues. 5or furt#er
co!parison, see t#e SM2 page.
After t#e boar #as been populate it !a$ be teste in a variet$ of 4a$s9
E#ile t#e po4er is off, visual inspection, automated optical
inspection. %E&E guielines for PCB co!ponent place!ent, solering, an
inspection are co!!onl$ use to !aintain 'uality control in t#is stage of PCB
!anufacturing.
E#ile t#e po4er is off, analog signature analysis, power(o) testing.
E#ile t#e po4er is on, in(circuit test, 4#ere p#$sical !easure!ents )for eCa!ple,
voltage* can be one.
E#ile t#e po4er is on, *unctional test, @ust c#ec1ing if t#e PCB oes 4#at it #a been
esigne to o.
2o facilitate t#ese tests, PCBs !a$ be esigne 4it# eCtra pas to !a1e te!porar$
connections. So!eti!es t#ese pas !ust be isolate 4it# resistors. 2#e in"circuit test
!a$ also eCercise bounar$ scan test features of so!e co!ponents. (n"circuit test
s$ste!s !a$ also be use to progra! nonvolatile !e!or$ co!ponents on t#e boar.
1
(n bounar$ scan testing, test circuits integrate into various (Cs on t#e boar for!
te!porar$ connections bet4een t#e PCB traces to test t#at t#e (Cs are !ounte
correctl$. Bounar$ scan testing re7uires t#at all t#e (Cs to be teste use a stanar test
configuration proceure, t#e !ost co!!on one being t#e ?oint 2est Action 8roup
)?2A8* stanar. 2#e ?2A8 test arc#itecture provies a !eans to test interconnects
bet4een integrate circuits on a boar 4it#out using p#$sical test probes. ?2A8 tool
venors provie various t$pes of sti!ulus an sop#isticate algorit#!s, not onl$ to
etect t#e failing nets, but also to isolate t#e faults to specific nets, evices, an pins.
E#en boars fail t#e test, tec#nicians !a$ esoler an replace faile co!ponents, a
tas1 1no4n as re4or1.
,.- Protection an) packa+in+
PCBs intene for eCtre!e environ!ents often #ave a confor!al coating, 4#ic# is
applie b$ ipping or spra$ing after t#e co!ponents #ave been solere. 2#e coat
prevents corrosion an lea1age currents or s#orting ue to conensation. 2#e earliest
confor!al coats 4ere 4aCI !oern confor!al coats are usuall$ ips of ilute solutions
of silicone rubber, pol$uret#ane, acr$lic, or epoC$. Anot#er tec#ni7ue for appl$ing a
confor!al coating is for plastic to be sputtere onto t#e PCB in a vacuu! c#a!ber. 2#e
c#ief isavantage of confor!al coatings is t#at servicing of t#e boar is renere
eCtre!el$ ifficult.
Man$ asse!ble PCBs are static sensitive, an t#erefore !ust be place in antistatic
bags uring transport. E#en #anling t#ese boars, t#e user !ust be groune
)eart#e*. (!proper #anling tec#ni7ues !ig#t trans!it an accu!ulate static c#arge
t#roug# t#e boar, a!aging or estro$ing co!ponents. <ven bare boars are
so!eti!es static sensitive. 2races #ave beco!e so fine t#at itGs 7uite possible to blo4
an etc# off t#e boar )or c#ange its c#aracteristics* 4it# a static c#arge. 2#is is
especiall$ true on non"traitional PCBs suc# as MCMs an !icro4ave PCBs.
PC/ characteristics
1
Muc# of t#e electronics inustr$Gs PCB esign, asse!bl$, an 7ualit$ control follo4s
stanars publis#e b$ t#e (PC organization.
,- Throu+h2hole technolo+!
Throughhole (leaded) resistors
2#e first PCBs use t#roug#"#ole tec#nolog$, !ounting electronic co!ponents
b$ leas inserte t#roug# #oles on one sie of t#e boar an solere onto copper traces
on t#e ot#er sie. Boars !a$ be single"sie, 4it# an unplate co!ponent sie, or
!ore co!pact ouble"sie boars, 4it# co!ponents solere on bot# sies.
&orizontal installation of t#roug#"#ole parts 4it# t4o aCial leas )suc# as resistors,
capacitors, an ioes* is one b$ bening t#e leas /0 egrees in t#e sa!e irection,
inserting t#e part in t#e boar )often bening leas locate on t#e bac1 of t#e boar in
opposite irections to i!prove t#e partGs !ec#anical strengt#*, solering t#e leas, an
tri!!ing off t#e ens. %eas !a$ be solere eit#er !anuall$ or b$ a 4ave
solering !ac#ine.
2#roug#"#ole PCB tec#nolog$ al!ost co!pletel$ replace earlier electronics asse!bl$
tec#ni7ues suc# as point"to"point construction. 5ro! t#e secon generation of
co!puters in t#e 1/+0s until surface"!ount tec#nolog$ beca!e popular in t#e late
1/.0s, ever$ co!ponent on a t$pical PCB 4as a t#roug#"#ole co!ponent.
2#roug#"#ole !anufacture as to boar cost b$ re7uiring !an$ #oles to be rille
accuratel$, an li!its t#e available routing area forsignal traces on la$ers i!!eiatel$
belo4 t#e top la$er on !ultila$er boars since t#e #oles !ust pass t#roug# all la$ers to
t#e opposite sie. Once surface"!ounting ca!e into use, s!all"size SMD co!ponents
1
4ere use 4#ere possible, 4it# t#roug#"#ole !ounting onl$ of co!ponents unsuitabl$
large for surface"!ounting ue to po4er re7uire!ents or !ec#anical li!itations, or
sub@ect to !ec#anical stress 4#ic# !ig#t a!age t#e PCB.
Throughhole de!ices mounted on the circuit board of a mid$%*+s home computer

A bo# of drill bits used for ma,ing holes in printed circuit boards. (hile tungstencarbide bits are !ery
hard, they e!entually wear out or brea,. -a,ing holes is a considerable part of the cost of a through
hole printed circuit board.
.- Surface2mount technolo+!
.urface mount components, including resistors, transistors and an integrated circuit
1
Surface"!ount tec#nolog$ e!erge in t#e 1/,0s, gaine !o!entu! in t#e earl$ 1/.0s
an beca!e 4iel$ use b$ t#e !i"1//0s. Co!ponents 4ere !ec#anicall$ reesigne
to #ave s!all !etal tabs or en caps t#at coul be solere irectl$ onto t#e PCB
surface, instea of 4ire leas to pass t#roug# #oles. Co!ponents beca!e !uc# s!aller
an co!ponent place!ent on bot# sies of t#e boar beca!e !ore co!!on t#an 4it#
t#roug#"#ole !ounting, allo4ing !uc# s!aller PCB asse!blies 4it# !uc# #ig#er
circuit ensities. Surface !ounting lens itself 4ell to a #ig# egree of auto!ation,
reucing labor costs an greatl$ increasing prouction rates. Co!ponents can be
supplie !ounte on carrier tapes. Surface !ount co!ponents can be about one"7uarter
to one"tent# of t#e size an 4eig#t of t#roug#"#ole co!ponents, an passive
co!ponents !uc# c#eaperI prices of se!iconuctor surface !ount evices )SMDs* are
eter!ine !ore b$ t#e c#ip itself t#an t#e pac1age, 4it# little price avantage over
larger pac1ages. So!e 4ire"ene co!ponents, suc# as 1='1'. s!all"signal s4itc#
ioes, are actuall$ significantl$ c#eaper t#an SMD e7uivalents.
1- Circuit properties of the PC/
<ac# trace consists of a flat, narro4 part of t#e copper foil t#at re!ains after etc#ing.
2#e resistance, eter!ine b$ 4it# an t#ic1ness, of t#e traces !ust be sufficientl$
lo4 for t#e current t#e conuctor 4ill carr$. Po4er an groun traces !a$ nee to be
4ier t#an signal traces. (n a !ulti"la$er boar one entire la$er !a$ be !ostl$ soli
copper to act as a groun plane for s#ieling an po4er return.
5or !icro4ave circuits, trans!ission lines can be lai out in t#e for! of strip line an
!icro strip 4it# carefull$ controlle i!ensions to assure a consistent i!peance. (n
raio"fre7uenc$ an fast s4itc#ing circuits t#e inuctance an capacitance of t#e
printe circuit boar conuctors beco!e significant circuit ele!ents, usuall$ unesireI
but t#e$ can be use as a eliberate part of t#e circuit esign, obviating t#e nee for
aitional iscrete co!ponents.
3- Materials
<Ccluing eCotic proucts using special !aterials or processes all printe circuit boars
!anufacture toa$ can be built using t#e follo4ing four !aterials9
1
%a!inates
Copper"cla la!inates
6esin i!pregnate B"stage clot# )Pre"preg*
Copper foil
o $aminates
%a!inates are !anufacture b$ curing uner pressure an te!perature la$ers of clot#
or paper 4it# t#er!oset resin to for! an integral final piece of unifor! t#ic1ness. 2#e
size can be up to ' b$ . feet )1.2 b$ 2.' !* in 4it# an lengt#. ;ar$ing clot# 4eaves
)t#reas per inc# or c!*, clot# t#ic1ness, an resin percentage are use to ac#ieve t#e
esire final t#ic1ness an ielectric c#aracteristics. Available stanar la!inate
t#ic1ness are liste in 2able 19
2able1
Stanar la!inate t#ic1ness per A=S(K(PC"D"2-+N2/O N=ote 1O
(PC %a!inat
e
=u!ber
2#ic1ness
in inc#es
2#ic1ness
in !illi!eters

(PC %a!inate
=u!ber
2#ic1ness
in inc#es
2#ic1ness
in !illi!eters
%1 0.002 0.0+ %/ 0.02. 0.-0
%2 0.00' 0.10 %10 0.03+ 0./0
%3 0.00, 0.1+ %11 0.0'3 1.10
%' 0.00. 0.20 %12 0.0++ 1.'0
%+ 0.010 0.2+ %13 0.0+/ 1.+0
%, 0.012 0.30 %1' 0.0-+ 1./0
%- 0.01, 0.'0 %1+ 0.0/0 2.30
%. 0.020 0.+0 %1, 0.122 3.10
.
1
2#e clot# or fiber !aterial use, resin !aterial, an t#e clot# to resin ratio eter!ine
t#e la!inateGs t$pe esignation )56"', C<M"1, 8"10, etc.* an t#erefore t#e
c#aracteristics of t#e la!inate prouce. (!portant c#aracteristics are t#e level to 4#ic#
t#e la!inate is fire retarant, t#e ielectric constant )er*, t#e loss factor )tP*, t#e tensile
strengt#, t#es#ear strengt#, t#e glass transition te!perature )2g*, an t#e Q"
aCis eCpansion coefficient )#o4 !uc# t#e t#ic1ness c#anges 4it# te!perature*.
2#ere are 7uite a fe4 ifferent ielectrics t#at can be c#osen to provie ifferent
insulating values epening on t#e re7uire!ents of t#e circuit. So!e of t#ese ielectrics
arepol$tetrafluoroet#$lene )2eflon*, 56"', 56"1, C<M"1 or C<M"3. Eell 1no4n
prepreg !aterials use in t#e PCB inustr$ are 56"2 )p#enolic cotton paper*, 56"3
)cotton paper an epoC$*, 56"' )4oven glass an epoC$*, 56"+ )4oven glass an
epoC$*, 56", )!atte glass an pol$ester*, 8"10 )4oven glass an epoC$*, C<M"1
)cotton paper an epoC$*, C<M"2 )cotton paper an epoC$*, C<M"3 )non"4oven glass
an epoC$*, C<M"' )4oven glass an epoC$*, C<M"+ )4oven glass an pol$ester*.
2#er!al eCpansion is an i!portant consieration especiall$ 4it# ball gri arra$ )B8A*
an na1e ie tec#nologies, an glass fiber offers t#e best i!ensional stabilit$.
56"' is b$ far t#e !ost co!!on !aterial use toa$. 2#e boar 4it# copper on it is
calle Jcopper"cla la!inateJ.
o Copper thickness
Copper t#ic1ness of PCBs can be specifie as units of lengt# )in !icro!eters or !ils*
but is often specifie as 4eig#t of copper per area )in ounce per s7uare foot* 4#ic# is
easier to !easure. One ounce per s7uare foot is 1.3'' !ils or 3' !icro!etres t#ic1ness.
2#e printe circuit boar inustr$ efines #eav$ copper as la$ers eCceeing 3 ounces of
copper, or approCi!atel$ 0.00'2 inc#es )'.2 !ils, 10+ R!* t#ic1. PCB esigners an
fabricators often use #eav$ copper 4#en esign an !anufacturing circuit boars in
orer to increase current"carr$ing capacit$ as 4ell as resistance to t#er!al strains.
&eav$ copper plate vias transfer #eat to eCternal #eat sin1s. (PC 21+2 is a stanar for
eter!ining current"carr$ing capacit$ of printe circuit boar traces.
Multi;ire *oar)s
1
Multi4ire is a patente tec#ni7ue of interconnection 4#ic# uses !ac#ine"route
insulate 4ires e!bee in a non"conucting !atriC )often plastic resin*. (t 4as use
uring t#e 1/.0s an 1//0s. )>oll!orgen 2ec#nologies Corp, 3.S. Patent
',1-+,.1, file 1/-.* Multi4ire is still available in 2010 t#roug# &itac#i. 2#ere are
ot#er co!petitive iscrete 4iring tec#nologies t#at #ave been evelope )?u!atec# ,
la$ere s#eets*.
Since it 4as 7uite eas$ to stac1 interconnections )4ires* insie t#e e!being !atriC,
t#e approac# allo4e esigners to forget co!pletel$ about t#e routing of 4ires )usuall$
a ti!e"consu!ing operation of PCB esign*9 An$4#ere t#e esigner nees a
connection, t#e !ac#ine 4ill ra4 a 4ire in straig#t line fro! one locationKpin to
anot#er. 2#is le to ver$ s#ort esign ti!es )no co!pleC algorit#!s to use even for
#ig# ensit$ esigns* as 4ell as reuce crosstal1 )4#ic# is 4orse 4#en 4ires run
parallel to eac# ot#erS4#ic# al!ost never #appens in Multi4ire*, t#oug# t#e cost is
too #ig# to co!pete 4it# c#eaper PCB tec#nologies 4#en large 7uantities are neee.
Cor);oo) construction
A cor4oo !oule
Cor4oo construction can save significant space an 4as often use 4it# 4ire"ene
co!ponents in applications 4#ere space 4as at a pre!iu! )suc# as !issile guiance
an tele!etr$ s$ste!s* an in #ig#"spee co!puters, 4#ere s#ort traces 4ere
i!portant. (n Jcor4ooJ construction, aCial"leae co!ponents 4ere !ounte
bet4een t4o parallel planes. 2#e co!ponents 4ere eit#er solere toget#er 4it# @u!per
1
4ire, or t#e$ 4ere connecte to ot#er co!ponents b$ t#in nic1el ribbon 4ele at rig#t
angles onto t#e co!ponent leas. 2o avoi s#orting toget#er ifferent interconnection
la$ers, t#in insulating cars 4ere place bet4een t#e!. Perforations or #oles in t#e
cars allo4e co!ponent leas to pro@ect t#roug# to t#e neCt interconnection la$er. One
isavantage of t#is s$ste! 4as t#at special nic1el"leae co!ponents #a to be use
to allo4 t#e interconnecting 4els to be !ae. Differential t#er!al eCpansion of t#e
co!ponent coul put pressure on t#e leas of t#e co!ponents an t#e PCB traces an
cause p#$sical a!age )as 4as seen in several !oules on t#e Apollo progra!*.
Aitionall$, co!ponents locate in t#e interior are ifficult to replace. So!e versions
of cor4oo construction use solere single"sie PCBs as t#e interconnection
!et#o )as picture*, allo4ing t#e use of nor!al"leae co!ponents.
Before t#e avent of integrate circuits, t#is !et#o allo4e t#e #ig#est possible
co!ponent pac1ing ensit$I because of t#is, it 4as use b$ a nu!ber of co!puter
venors incluing Control Data Corporation. 2#e cor4oo !et#o of construction
4as use onl$ rarel$ once se!iconuctor electronics an PCBs beca!e 4iesprea.
Pc* Materials
,- Con)uctie ink
GConuctive in1G is an in1 t#at results in a printe ob@ect 4#ic# conucts electricit$. 2#e
transfor!ation fro! li7ui in1 to soli printing !a$ involve r$ing, curing or !elting
processes.
2#ese in1s !a$ be classe as fire #ig# solis s$ste!s or P25 pol$!er t#ic1 fil!
s$ste!s t#at allo4 circuits to be ra4n or printe on a variet$ of substrate !aterials
suc# as pol$ester to paper. 2#ese t$pes of in1s usuall$ contain conuctive !aterials
suc# as po4ere or fla1e silver an carbon li1e !aterials, alt#oug# pol$!eric
conuction is also 1no4n.
Conuctive in1s can be a !ore econo!ical 4a$ to la$ o4n a !oern conuctive
traces 4#en co!pare to traitional inustrial stanars suc# as etc#ing
1
copper fro! copper plate substrates to for! t#e sa!e conuctive traces on relevant
substrates, as printing is a purel$ aitive process proucing little to no 4aste strea!s
4#ic# t#en #ave to be recovere or treate.
Silver in1s #ave !ultiple uses toa$ incluing printing 65(D tags as use in
!oern transit tic1ets, t#e$ can be use to i!provise or repair circuits on printe circuit
boars.Co!puter 1e$boars contain !e!branes 4it# printe circuits t#at sense 4#en a
1e$ is presse. Eins#iel efrosters consisting of resistive traces applie to t#e glass
are also printe. Man$ ne4er cars #ave conuctive traces printe on a rear 4ino4,
serving as t#e raio antenna.
Printe paper an plastic s#eets #ave proble!atic c#aracteristics, pri!aril$ #ig#
resistance an lac1 of rigiit$. 2#e resistances are too #ig# for t#e !a@orit$ of circuit
boar 4or1, an t#e non"rigi nature of t#e !aterials per!its unesirable forces to be
eCerte on co!ponent connections, causing reliabilit$ proble!s. Conse7uentl$ suc#
!aterials are onl$ use in a restricte range of applications, usuall$ 4#ere t#e
fleCibilit$ is i!portant an no parts are !ounte on t#e s#eet.
.- /T2Epox!
B2"<poC$ belongs to t#e group of t#er!oset resins use in printed circuit
boards )PCBs*. (t is a !iCture of epo+y resin, a co!!on ra4 !aterial for PCBs an
B2 resins. B2 stans for Bis!alei!ie"2riazine resin. 2#is is in turn a !iCture
of bismaleimide, 4#ic# as suc# is also use as a ra4 !aterial for PCBs an cyanate
ester. 2#ree c$ano groups of t#e c$anate ester are trimeri,ed to a tria,ine ring
structure, #ence t#e 2 in t#e na!e. (n presence of a bis!alei!ie t#e ouble bon of
t#e !alei!ie group can copolymeri,e 4it# t#e cyano groups to heterocyclic ,"
!e!bere aromatic ring structures 4it# t4o nitrogen ato!s )pyrimidines*. 2#e cure
reaction occurs at te!peratures up to 2+0 egrees C, an is catal$ze b$ strongl$ basic
!olecules li1e Dabco )iazabic$clooctane* an '"DMAP )'"i!et#$la!inop$riin*.
Proucts 4it# ver$ #ig# glass transition te!peratures )2g*" up to 300 egrees C " an
ver$ lo4 ielectric constant can be obtaine. 2#ese properties !a1e t#ese !aterials
ver$ attractive for use in PCBs.
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1- Composite epox! material
Co!posite <poC$ Materials )C<M* are a group of co!posite !aterials t$picall$ !ae
of 4oven glass fabric surfaces an non"4oven glass core co!bine 4it# epoC$ resin.
2#e$ are t$picall$ use in printe circuit boars.
2#ere are ifferent t$pes of C<Ms9
C<M"1 is lo4 cost, fla!e retarant, cellulose paper base la!inate 4it# onl$ one la$er
of 4oven glass fabric.
C<M"2 #as cellulose paper core an 4oven glass fabric surface.
C<M"3 is ver$ si!ilar to t#e !ost co!!onl$ use PCB !aterial, 56'. (ts color is
4#ite an it is fla!e retarant.
C<M"' 7uite si!ilar as C<M"3 but not fla!e retarant.
C<M"+ )also calle C6M"+* #as pol$ester 4oven glass core.
3- C!anate ester
C$anate esters are c#e!ical substances generall$ base on a bisp#enol or novolac
erivative, in 4#ic# t#e #$rogen ato! of t#e p#enolic O& group is substitute b$
a c$aniegroup. 2#e resulting prouct 4it# an "OC= group is na!e a c$anate ester.
C$anate esters can be cure an postcure b$ #eating, eit#er alone at elevate
te!peratures or at lo4er te!peratures in presence of a suitable catal$st. 2#e !ost
co!!on catal$sts are transition !etal co!pleCes of cobalt, copper, !anganese an
zinc. 2#e result is a t#er!oset !aterial 4it# a ver$ #ig# glass"transition
te!perature )2g* of up to '00 TC, an a ver$ lo4 ielectric constant, proviing
eCcellent long ter! t#er!al stabilit$ at elevate en use te!peratures, ver$ goo fire,
s!o1e an toCicit$ perfor!ance an specific suitabilit$ for printe circuit
1
boars installe in critical electrical evices. 2#is is also ue to its lo4 !oisture
upta1e. 2#is propert$, toget#er 4it# a #ig#er toug#ness co!pare to epoCies, also
!a1es it a valuable !aterial in aerospace applications. 5or eCa!ple t#e %$nC Mar1
(( spaceplane is pri!aril$ !ae of carbonKc$anate ester.
2#e c#e!istr$ of t#e cure reaction is a tri!erization of t#ree C= groups to
a triazine ring. Because t#e starting !aterial is a prouct 4it# t4o c$anate groups t#e
resulting structure is a 3D pol$!er net4or1. Prouct properties can be finetune b$ t#e
c#oice of substituents in t#e bisp#enolic co!poun. Bisp#enol"A an novolac base
c$anate esters are t#e !a@or proucts, bisp#enol"5 an bisp#enol"< are also use. 2#e
aro!atic ring of t#e bisp#enol can be substitute 4it# an all$lic group for i!prove
toug#ness of t#e !aterial. C$anate esters can also be !iCe 4it# bis!alei!ies to
for! B2"resins or 4it# epoC$ resins to opti!ize t#e en use properties
5- <&2.
56"2 is an abbreviation for 5la!e 6esistant 2. (t is a $EM- esignation for s$nt#etic
resin bone paper, a composite material !ae of paper i!pregnate 4it# a
plasticizephenol *ormaldehyde resin, use in t#e !anufacture of printed circuit
boards. (ts !ain properties are si!ilar to =<MA grae UUUP )M(%"P"311+* !aterial,
an can be substitute for t#e latter in !an$ applications.
6- <&23
56"' )or 56'* is a grae esignation assigne to glass"reinforce epoC$ la!inate
s#eets, tubes, ros an printe circuit boars )PCB*. 56"' is a co!posite !aterial
co!pose of 4oven fiberglass clot# 4it# an epoC$ resin biner t#at is fla!e
resistant )self"eCtinguis#ing*.
J56J stans for fla!e retarant, an enotes t#at safet$ of fla!!abilit$ of 56"' is in
co!pliance 4it# t#e stanar 3%/';"0. 56"' is create fro! t#e constituent !aterials
1
)epoC$ resin, 4oven glass fabric reinforce!ent, bro!inate fla!e retarant, etc.*
b$ =<MA in 1/,..
56"' glass epoC$ is a popular an versatile #ig#"pressure t#er!oset plastic la!inate
grae 4it# goo strengt# to 4eig#t ratios. Eit# near zero 4ater absorption, 56"' is
!ost co!!onl$ use as an electrical insulator possessing consierable !ec#anical
strengt#. 2#e !aterial is 1no4n to retain its #ig# !ec#anical values an electrical
insulating 7ualities in bot# r$ an #u!i conitions. 2#ese attributes, along 4it# goo
fabrication c#aracteristics, len utilit$ to t#is grae for a 4ie variet$ of electrical an
!ec#anical applications.
=<MA is t#e regulating aut#orit$ for 56"' an ot#er insulating la!inate graes. 8rae
esignations for glass epoC$ la!inates are9 810, 811, 56' an 56+. Of t#ese, 56' is
t#e grae !ost 4iel$ in use toa$. 8"10, t#e preecessor to 56"', lac1s 56"'Gs self"
eCtinguis#ing fla!!abilit$ c#aracteristics. &ence, 56"' #as since replace 8"10 in
!ost applications.
56"' epoC$ resin s$ste!s t$picall$ e!plo$ bro!ine, a #alogen, to facilitate fla!e"
resistant properties in 56"' glass epoC$ la!inates. So!e applications 4#ere t#er!al
estruction of t#e !aterial is a esirable trait 4ill still use 8"10 non fla!e resistant



PC/ DESI(NIN(
1
PCB stans for AP6(=2<D C(6C3(2 BOA6DB. Printe circuit boar )PCB* provies
bot# t#e p#$sical structure for !ounting an #oling t#e co!ponents as 4ell as t#e
electrical interconnection bet4een t#e co!ponents. 2#at !eans a PCB V PEB )printe
4iring boar* is t#e platfor! upon 4#ic# electronic co!ponents suc# as integrate
circuit c#ips an ot#er co!ponents are !ounte. A PCB consists of a non"conucting
substrate )t$picall$ fiber glass 4it# epoC$ as resin* upon 4#ic# t#e conuctive pattern
or circuitr$ is for!e. Copper is t#e !ost prevalent conuctor alt#oug# nic1el, silver
an tin are also use in so!e cases.
T!pes of PC/
PCB !a$ be of ifferent t$pes9"
1* Single"sie
2* Double"sie
3* Multila$er
Sin+le si)e) PC/s9 " As t#e na!e suggest in t#ese esigns t#e conuctive pattern is
onl$ at in one sie. An also t#e size is large in t#ese case but t#ese are c#eap.
Dou*le si)e) PC/s9 " 2#ese are t#e PCBs on 4#ic# t#e conuctive pattern is in on
bot# sies. 2#e size of boar is s!all in t#is case but it is costlier t#an t#at of above.
Multila!er PC/s= 2 (n t#is case t#e boar consists of alternating la$ers of conucting
pattern an insulating !aterial. 2#e conuctive !aterial is connecte across t#e la$ers
t#roug# plate t#roug# #oles. 2#e size of t#is PCB is s!aller t#an t#at of ouble sie
PCB but it is ver$ costl$.
PCBs !a$ also be eit#er rigi, fleCible, or t#e co!bination of t4o )rigi"fleC*. E#en
t#e electronic co!ponents #ave been !ounte on t#e PCB, t#e co!bination of PCB
an co!ponents is an electronic asse!bl$, also calle P6(=2<D C(6C3(2
ASS<MB%W. 2#is asse!bl$ is t#e basic builing bloc1 for all t#e electronic appliances
suc# as television, co!puter an ot#er goos.
<UNCTIONS O< PC/
1
Printe circuite boars are ielectric substrates 4it# !etallic circuitr$ for!e on t#at.
2#e$ are so!eti!es referre to as t#e base line in electronic pac1aging. <lectronic
pac1aging is funa!entall$ an inter connection tec#nolog$ an t#e PCB is t#e baseline
builing bloc1 of t#is tec#nolog$.
TEC#NI>UES USED <O& PC/ DESI(NIN(
2#ere !ainl$ t4o tec#ni7ues 4#ic# are use for t#e PCB esigns.
1. &an 2aping
2. Co!puter Aie Design
1* PCBs using &an 2aping9
o PCB esign using #an taping is t#e process of tec#nical
ra4ing.
o (n #an taping !et#o la$out s#oul be prepare on gri paper.
o (n #an taping, co!ponents pas can be prepare b$ using blac1
pas.
o 6outing of t#e boar can be one b$ tapes 4it# ifferent 4it#s.
<ac# la$er )top, botto!* #as to prepare separatel$.
DIS%D?%NT%(S O< #%ND2T%PIN( <O& PC/ DESININ(=
<ac# la$er #as to be esigne Sep
Ee cannot generate =CD files for C=C rilling.
Difficult to !oif$ t#e esign in t#e esigning process or after esigning.
2* PCB D<S(8=(=8 3S(=8 CAD
All t#e above ifficulties can be re!ove b$ using CAB s$ste!.
1
CAD s$ste! for PCB esigning re7uires follo4ing9
o A co!puter s$ste!.
o PCB esign soft4are li1e OrCa, CADS2A6, Protel, 2A=8O, Mentor
etc.
o A p#oto plotter for art 4or1 generation.
2#ere are !an$ en#ance features in electronics esign auto!ation tools 4#ic# not
possible in t#e #an taping. 2#e !ain avantages are given belo49
o Auto place!ent
o Auto routing
o After routing, opti!ization of trac1s can be one.
o Provies p#$sical esign reuse !oules
o <lectrical rule c#ec1 )<6C*
o All t#e la$ers are generate fro! t#e sa!e esign b$ giving ifferent
options.
o Bill of !aterial can be generate 4#ic# contains nu!ber of ifferent
co!ponents use.
o Ee can ra4 conuctors as an arc, se!i"circular at ifferent angles.
o Design 6ule C#ec1
o Avance CAD s$ste!s #ave #ig# spee anal$sis.
o CAD s$ste! provies all =CD files an 8erber ata files for p#oto
plotting.
/%SIC DESI(N STEPS IN C%D2 S@STEM
2#e follo4ing esign steps are ver$ co!!on 4#ile esigning a PCD in CAD9
<ntr$ t#e sc#e!atic iagra!.
=et list file creation.
Place!ent of co!ponents !anuall$ or auto!aticall$.
6outing of t#e boar using !anual routing tools or auto router
Design rule c#ec1 p#$sical an electrical.
1
Art4or1 generation.
OrCa) Desi+n Enironment
OrCa #as a long #istor$ of proviing iniviuals an tea!s 4it# a co!plete set of
tec#nologies t#at offer unpreceente prouctivit$, sea!less tool integration, an
eCceptional value. =e4 10.+ releases continue t#at traition. 2oa$Ds lo4er cost an $et
#ig#l$ sop#isticate electronic esign auto!ation s$ste!s #ave create a uni7ue
c#allenge to nearl$ ever$ engineering epart!ent. 2#erefore t#e use of <DA tools #as
beco!e increasingl$ i!portant as prouct lifec$cles #ave beco!e s#orter an s#orter.
Moern electronic esign auto!ation )<DA* tools are beginning to support a !ore
efficient an integrate approac# to electronic. OrCa CaptureX esign entr$ is t#e
!ost 4iel$ use sc#e!atic entr$ s$ste! in electronic esign toa$ for one si!ple
reason9 fast an universal esign entr$. E#et#er $ouGre esigning a ne4 analog circuit,
revising sc#e!atic iagra! for an eCisting PCB, or esigning a igital bloc1 iagra!
4it# an &D% !oule, OrCa Capture provies si!ple sc#e!atic co!!ans $ou nee
to enter, !oif$ an verif$ t#e esign for PCB. OrCa %a$out X offers PCB esigners
an PCB esign tea!s t#e po4er an fleCibilit$ to create an s#are PCB ata an
constraints across t#e esign flo4. OrCa %a$out elivers all t#e capabilities to
esigners nee fro! netlist to place an route, to final output. 2#e ease"of use an
intuitive capabilities of OrCa %a$out
PC/ DESI(N STEPS IN OrCa) 9.,
Entr! of Schematic Dia+ram
Sc#e!atic iagra! provies t#e functional flo4 an t#e grap#ical representation of an
electronic circuit. 2#e entr$ of sc#e!atic iagra! is t#e first step in PCB esign using
OrCa.
A sc#e!atic iagra! consists of9"
<lectrical connections)nets*
?unctions
1
(ntegrate circuits s$!bols
Discrete co!ponents s$!bols li1e resistors, capacitors etc.
(nput K output connectors
Po4er an groun s$!bols
Buses
=o connection s$!bols
Co!ponents reference na!es
2eCt
The Schematic Pa+e E)itor=
2#e sc#e!atic page eitor is use to ispla$ an eit sc#e!atic pages. So t#at one can
partsI 4iresI buses an ra4 grap#ics. 2#e sc#e!atic page eitor #as a tool palette t#at
4e can use to ra4 an place ever$t#ing 4e nee to create a sc#e!atic page. One can
print fro! 4it#in t#e sc#e!atic page eitor, or fro! t#e pro@ect 4ino4.
1
Startin+ Capture
2#e OrCAD 6elease / installation process puts Capture in t#e YP6O86AM
5(%<SYO6CADYCAP236< foler, an as AOrCAD 6elease /B to t#e Progra!s !enu
)available fro! t#e Start button*.
To start Capture
5ro! t#e Start !enu, c#oose Progra!s. 2#e Progra!s !enu ispla$s.
5ro! t#e OrCAD 6elease / !enu ite!, c#oose Capture.
The Capture session frame
Once 4e start Capture, 4e see t#e Capture session fra!e 4e o all $our sc#e!atic
esign an processing 4it#in t#is 4ino4. 2#e !ini!ize Session %og icon in t#e lo4er
left portion of t#e Capture session fra!e is t#e session log. 2#e session log provies
infor!ation about ever$t#ing 4e #ave one in t#e current Capture session. Detaile
infor!ation about t#is 4ino4San t#e ot#er 4ino4s in Capture.
1
The Capture ;ork enironment
(n Capture, eac# esign t#at 4e open is in a separate pro@ect !anager 4ino4. (f 4e
nee to 4or1 si!ultaneousl$ 4it# several esigns, 4e can open t#e! all, an eac# 4ill
#ave its o4n pro@ect !anager 4ino4. Depening on 4#ic# t$pe of 4ino4 4e #ave
active)an active 4ino4 is one 4#ose title bar is #ig#lig#te*, certain buttons on t#e
toolbar an certain ite!s on t#e !enus !a$ be unavailable, since 4e perfor! tas1s an
use tools base upon t#e t$pe of 4ino4 t#at is active. Also, t#e !enus an !enu
c#oices var$, epening on 4#ic# t$pe of 4ino4 is active. 2#e available !enus an
!enu c#oices 4ill also var$ epening upon t#e t$pe of pro@ect $ou are 4or1ing 4it#.
(t s#o4s t#e 4ino4s 4e see in Capture9 t#e pro@ect !anager, t#e sc#e!atic page see in
Capture9 t#e pro@ect !anager, t#e sc#e!atic page eitor, t#e part eitor, t#e teCt eitor,
an t#e session log. (t also introuces 4e to t#e toolbar, tool palettes, an general
Capture concepts suc# as selecting an eiting ob@ects, eiting properties, an unoing
an repeating actions.
The proAect mana+er
4e use t#e pro@ect !anager to collect an organize all t#e resources 4e nee for our
pro@ect. 2#ese resources inclue sc#e!atic folers, sc#e!atic pages, part libraries, parts,
;&D% files, an output reports suc# as bills of !aterials an netlists.
A pro@ect oesnDt actuall$ contain all t#e resources. (t !erel$ Apoints toB t#e various files
t#at t#e pro@ect uses.
5or t#is reason, 4e onDt !ove or elete an$ files reference b$ a pro@ect. (f 4e o, t#e
pro@ect 4onDt be able to fin t#e!. 2#e pro@ect file is save 4it# an .OP? file eCtension.
(t is an ASC(( file, an can be vie4e in an$ teCt eitor.
ProAect mana+er fol)ers
1
2#e pro@ect !anager provies a grap#ical ispla$ of a pro@ectDs resources b$ grouping
t#e! into appropriate folers.
Design 6esources foler is t#e esign foler 4it# t#e esignDs sc#e!atic folers an
sc#e!atic pages, an a Design Cac#e foler t#at s#o4s all t#e parts use on t#e
sc#e!atic pages. An$ sc#e!atic folers or sc#e!atic pages t#at 4e create are
auto!aticall$ ae to t#e esign foler )in 5ig. t#e esign foler is na!e
D<S(8=3.DS=*. 4e can also a ot#er files or infor!ation using t#e Pro@ect co!!an
on t#e <it !enu
2#e %ibrar$ foler )in t#e Design 6esources foler* s#o4s t#e sc#e!atic part librar$
files 4eDve ae to t#e pro@ect using t#e Pro@ect co!!an on t#e <it !enu.
2#e Outputs foler s#o4s t#e output of CaptureDs processing tools. 8enerall$, t#ese files
inclue bill of !aterials reports an tec#nolog$"specific netlists Capture as t#e
appropriate files to t#is foler as eac# is create.
<ac# pro@ect !a$ #ave onl$ one esign, but !a$ #ave !ultiple libraries. 2#e esign !a$
consist of an$ nu!ber of sc#e!atics or ;&D% !oels, but it !ust #ave a single root
module
2#e root !oule is efine as t#e top level of t#e esign. 2#at is, all ot#er !oules in
t#e esign are reference 4it#in t#e root !oule.
1
Eit#in t#e pro@ect !anager, 4e can eCpan or collapse t#e structure 4e see b$ ouble"
clic1ing on a foler, or b$ clic1ing on t#e plus sign or !inus sign to t#e left of a foler.
A plus sign inicates t#at t#e foler #as contents t#at are not currentl$ visibleI a !inus
sign inicates t#at t#e foler is open an its contents are visible, liste belo4 t#e foler.
(t appears as a sc#e!atic foler 4it# a slas# on it in a esign file, or as a page in a
;&D% file.
<ac# pro@ect 4e open #as its o4n pro@ect !anager 4ino4. 4e can !ove or cop$ folers
or files bet4een pro@ects b$ ragging t#e! fro! one pro@ect !anager 4ino4 to anot#er
)as 4ell as to an fro! Eino4s <Cplorer*. 2o cop$ rat#er t#an !ove ite!s, press an
#ol t#e C 1e$ 4#ile 4e rag t#e!. (f 4e close a pro@ect !anager 4ino4, 4e close t#e
pro@ect.
(n t#e pro@ect !anagerDs 5ile tab, ouble"clic1ing on a sc#e!atic foler eCpans it an
ispla$s icons for eac# sc#e!atic page 4it#in t#e sc#e!atic foler. 2#en, if 4e ouble"
clic1 on a sc#e!atic page icon, t#e sc#e!atic page opens in a sc#e!atic page eitor. Or,
if t#e page is alrea$ open, its 4ino4 beco!es active.
A esign can consist of a single sc#e!atic page 4it#in a single sc#e!atic foler, or a
nu!ber of sc#e!atic pages 4it#in a nu!ber of sc#e!atic folers. A sc#e!atic foler
AcontainsB sc#e!atic pages in a relations#ip si!ilar to t#e relations#ip bet4een a
irector$ an t#e files it contains. 5iles are containe in a irector$I sc#e!atic pages are
containe in a sc#e!atic foler.
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A sc#e!atic page provies a grap#ical escription of t#e electrical connectivit$ of a
esign. (t is !ae up of parts, 4ires, an ot#er electrical s$!bols. A sc#e!atic page !a$
also contain borers, title bloc1s, teCt, an grap#ics. Capture acts on an$ sc#e!atic
folers or sc#e!atic pages 4e #ave selecte 4it#in an active pro@ect !anager 4ino4.
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5or eCa!ple, t#e 5in an Bro4se co!!ans on t#e pro@ect !anagerDs <it !enu, t#e
Print co!!an on t#e pro@ect !anagerDs 5ile !enu, an t#e various tools on t#e 2ools
!enu, onl$ appl$ to t#e selecte sc#e!atic foler or page.
ProAect mana+er ta*sB<ile an) #ierarch!
2#e pro@ect !anager provies t4o 4a$s to ispla$ a pro@ectDs resources. (f 4e c#oose
t#e 5ile tab, t#e pro@ect !anager ispla$s all t#e pro@ectDs folers, sc#e!atic folers, an
sc#e!atic pages. 2#ese are ispla$e in a tree"li1e fas#ion. 4e can eCpan or collapse
t#e tree b$ clic1ing t#e plus sign in front of t#e icon. E#en t#at branc# of t#e tree is
eCpane, t#e plus sign c#ange to a !inus sign. (f 4e c#oose t#e &ierarc#$ tab, t#e
pro@ect !anager ispla$s t#e #ierarc#ical relations#ip a!ong t#e pro@ectDs sc#e!atic
folers an sc#e!atic pages.
Sin+le ie;
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;ersions of Capture prior to 6elease / use logical !oe an p#$sical !oe to separate
instance an occurrence infor!ation. =o4, bot# instances an occurrences are containe
in a single vie4. 2#e pro@ect !anager s#o4s all occurrences in t#e &ierarc#$ tab.
(n versions of Capture prior to 6elease /, it 4as necessar$ to s4itc# !oes before
creating a netlist for use 4it# OrCAD %a$out. =o4, t#e netlist tool provies an option to
use eit#er t#e instance properties or t#e occurrence properties for creating a netlist.
The schematic pa+e e)itor
2#e sc#e!atic page eitor is use to ispla$ an eit sc#e!atic pages. Ee can place
parts, 4ires, buses, an ra4 grap#ics. 2#e sc#e!atic page eitor #as a tool palette t#at
4e can use to ra4 an place ever$t#ing 4e nee to create a sc#e!atic page. 4e can
print fro! 4it#in t#e sc#e!atic page eitor, or fro! t#e pro@ect !anager 4ino4.
Schematic pa+e e)itor
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The part e)itor
2#e part eitor is use to create an eit parts.
5ro! t#e ;ie4 !enu of t#e part eitor $ou can c#oose eit#er Part or Pac1age. (n
Part vie4 4e can9
Create an eit parts an s$!bols, t#en store t#e! in ne4 or eCisting libraries.
Create an eit po4er an groun s$!bols, off"page connector s$!bols, an title
bloc1s.
3se t#e tool paletteDs electrical tools to place pins on parts, an its ra4ing tools
to ra4 parts an s$!bols.
Pac1age vie4 s#o4s t#e entire pac,age. A pac1age is a p#$sical part t#at
contains !ore t#an one logical part. Ee can eit t#e properties of t#e entire
pac1age, suc# as part reference, prefiC, part alias, an so on. Ee cannot eit
iniviual parts in t#is vie4, but 4e can select iniviual parts to eit b$ ouble"
clic1ing on t#e!.
2#e part eitor is ver$ si!ilar to t#e s$!bol eitor.
2#e !ain ifference bet4een t#e t4o is t#e s$!bol eitorDs lac1 of Pin an Pin
Arra$ tool palette buttons.
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The session lo+
2#e session log lists t#e events t#at #ave occurre uring t#e current Capture
session, incluing !essages resulting fro! using CaptureDs tools. 2o ispla$
conteCt"sensitive #elp for an error !essage, put t#e cursor in t#e error !essage
line in t#e session log an press 2#e ruler along t#e top appears in eit#er inc#es or
!illi!eters, epening on 4#ic# !easure!ent s$ste! )3.S. or Metric* is selecte
in t#e Eino4s Control Panel. 4e can a tab settings to t#e ruler b$ clic1ing in
t#e ruler bar, ragging t#e tabs to ifferent positions, or re!ove t#e! b$ ragging
t#e! o4n into t#e session log 4ino4. our tab settings are save an use eac#
ti!e 4e start Capture.
4e can searc# for infor!ation in t#e session log using t#e 5in co!!an on t#e
<it !enu. Ee can also save t#e contents of t#e session log to a file, 4#ic# is
useful 4#en 4or1ing 4it# OrCADDs tec#nical support staff to solve tec#nical
proble!s. 2#e efault filena!e is S<SS(O=.2U2.
To )ispla! the session lo+
Clic1 on t#e session logDs !aCi!ize button, or c#oose Session %og fro! t#e Eino4
!enu.
To minimi0e the session lo+
Clic1 t#e !ini!ize button on t#e title bar.
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To cop! session lo+ text to the Clip*oar)
Select t#e session log 4ino4 to !a1e it active.
Select t#e teCt an c#oose Cop$ fro! t#e <it !enu.
To print the session lo+
Select t#e session log 4ino4 to !a1e it active.
5ro! t#e 5ile !enu, c#oose t#e Print co!!an.
To use <in) in the session lo+
Select t#e session log 4ino4 to !a1e it active.
5ro! t#e <it !enu, c#oose t#e 5in co!!an. 2#e 5in ialog boC appears.
<nter t#e 4or or 4ors t#at 4e 4ant to fin.
Clic1 5in =eCt.
To sae the session lo+ to a text file
Select t#e session log 4ino4 to !a1e it active.
5ro! t#e 5ile !enu, c#oose t#e Save As co!!an. 2#e Save As ialog boC appears.
<nter a file na!e in t#e 5ile na!e teCt boC. B$ efault, t#e session log is save to
S<SS(O=.2U2 in t#e current irector$. (f necessar$, specif$ a ne4 location for t#e file.
Clic1 Save. 2#e session log teCt is save to t#e file.
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The tool*ar
2#e toolbar is al4a$s oc1e on t#e top ege of t#e session fra!e t#e first ti!e
4e open a pro@ect in a ne4 session fra!e of Capture. 2#e position of t#e tool palette is
not save.
CaptureDs toolbar is doc,able)t#at is, 4e can select an area bet4een buttons an rag t#e
toolbar to a ne4 location* an resizable, an ispla$s tooltips for eac# tool. B$ c#oosing
a tool button, 4e can 7uic1l$ perfor! a tas1. (f a tool button is i!!e, 4e canDt
perfor! t#at tas1 in t#e current situation.
The part e)itor tool palette
2#e first group of tools on t#e part eitor tool palette is electrical tools, use to place
pins an (<<< s$!bols. 2#e secon group of tools is ra4ing tools, use to create
grap#ical ob@ects 4it#out electrical connectivit$
Startin+ a proAect
A pro@ect files ).OP?* stores pointers to a single esign file ).DS=*, an can also contain
libraries, ;&D% files, an output reports associate 4it# t#e esign file. A esign file
contains one or !ore sc#e!atic folers, in 4#ic# t#ere are one or !ore sc#e!atic pages.
A esign file also contains a esign cac#e,
E#ic# is li1e an e!bee librar$" it contains a cop$ of all t#e parts an s$!bols use
on t#e sc#e!atic pagesZ E#en a esign is save 4it# t#e pro@ect file, infor!ation fro!
t#e various 2ools ialog boCes is also save in t#e pro@ect file.
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Creatin+ ne; proAects")esi+ns" li*raries
4e can create a ne4 pro@ect, an t#en create ne4 esigns, libraries.
To create a ne; proAect
5ro! t#e 5ile !enu, c#oose =e4, t#en c#oose Pro@ect. 2#e =e4 Pro@ect ialog
boC appears.
2$pe a na!e for our ne4 pro@ect in t#e =a!e teCt boC
3se t#e Bro4se button to select a ne4 irector$.
Select a pro@ect t$pe in t#e Create a =e4 Pro@ect 3sing group boC, an clic1 O>.
Capture provies t#e follo4ing pro@ect t$pes9
%nalo+ or mixe) si+nal circuitSselects t#is t$pe of pro@ect if 4e inten to use $our
esign 4it# OrCAD PSpice. 5ollo4 t#e guiance of t#e Analog MiCe"Moe Pro@ect
4izar to a t#e appropriate files to pro@ect.
PC *oar)Bselect t#is t$pe of pro@ect if 4e inten to use our esign 4it# OrCAD
%a$out. 5ollo4 t#e guiance of t#e PCB Pro@ect Eizar to a t#e appropriate files .
Pro+ramma*le lo+icBselects t#is t$pe of pro@ect if 4e inten to use our esign 4it# Or
CAD <Cpress. 5ollo4 t#e guiance of t#e Progra!!able %ogic Pro@ect Eizar to a
t#e appropriate files to our pro@ect.
SchematicBselect t#is t$pe of pro@ect if none of t#e ot#er pro@ect t$pes appl$. 3sing
t#is option, Capture creates a basic pro@ect containing onl$ t#e esign file.
To create a ne; )esi+n
5ro! t#e 5ile !enu, c#oose =e4, t#en c#oose Design.
2#e esign opens in a ne4 PCB pro@ect !anager an a ne4 sc#e!atic page
ispla$s.
To create a ne; schematic pa+e
On t#e 5ile tab of t#e pro@ect !anager, select t#e sc#e!atic foler t#at re7uires a
ne4 sc#e!atic page.
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Clic1 t#e rig#t !ouse button an c#oose =e4 Page fro! t#e pop"up !enu. A
ne4 sc#e!atic page appears 4it#in t#e sc#e!atic foler 4e selecte in step 1.
To create a ne; li*rar!
5ro! t#e 5ile !enu, c#oose =e4, t#en c#oose %ibrar$
2#e librar$ opens in t#e pro@ect !anager an a %ibrar$ Cac#e foler is ae to
t#e pro@ect !anager, or t#e librar$ opens in t#e eCisting open pro@ect !anager
an a librar$ cac#e is ae.
Openin+ existin+ proAects" )esi+ns" an) li*raries
4e can open an eCisting pro@ect, esign, librar$ or ;&D% file. <Cisting sc#e!atic
pages can onl$ be opene fro! 4it#in esigns an libraries
To open an existin+ proAect
5ro! t#e 5ile !enu, c#oose Open, an t#en c#oose Pro@ect. 2#e Open Pro@ect ialog
boC ispla$s.
Select a pro@ect ).OP?* or t$pe t#e na!e in t#e 5ile na!e teCt boC, t#en c#oose t#e Open
button. 2#e pro@ect opens in t#e pro@ect !anager.
To open an existin+ )esi+n
5ro! t#e 5ile !enu, c#oose Open, an t#en c#oose Design 2#e Open Design ialog boC
ispla$s.
Select a esign ).DS=* or t$pe t#e na!e in t#e 5ile na!e teCt boC, t#en c#oose t#e Open
button. 2#e esign opens in t#e pro@ect !anager.
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1
To open an existin+ schematic pa+e
(n t#e pro@ect !anager, select t#e 5ile tab an ouble"clic1 t#e icon of a sc#e!atic
folerI t#is <Cpans t#e foler an reveals t#e sc#e!atic pages it contains.
Double"clic1 on t#e icon of t#e sc#e!atic page 4e 4ant to open. 2#e sc#e!atic page
opens in a sc#e!atic page eitor 4ino4.
To open an existin+ li*rar!
1 5ro! t#e 5ile !enu, c#oose Open, t#en c#oose %ibrar$. 2#e Open %ibrar$
ialog boC ispla$s.
2 Select a librar$ ).O%B* or t$pe t#e na!e in t#e 5ile na!e teCt boC, an t#en
c#oose t#e Open button. 2#e librar$ opens in t#e pro@ect !anager.
'orkin+ ;ith files in a proAect
3sing t#e pro@ect !anager, 4e can a or elete pro@ect files. 4e can a an$ file to our
pro@ect, incluing libraries an ;&D% files. 5iles not in ASC(( for!at, or a Capture
generate for!at, !a$ not appear as eCpecte 4#en opene in Capture.
To a)) a file to proAect
1
1 (n t#e pro@ect !anager, select t#e foler to 4#ic# 4e 4ant to a a file.
2 5ro! t#e <it !enu c#oose Pro@ect. 2#e A 5ile to Pro@ect 5oler ialog boC
ispla$s.
3 Select t#e file 4e 4ant to a an c#oose t#e Open button. 2#e file is ae to t#e
pro@ect.
Or
1 Drag t#e file fro! t#e Eino4s <Cplorer into t#e foler in t#e pro@ect !anager.
To )elete a file from a proAect
1 (n t#e pro@ect !anager, select t#e file 4e 4ant to elete.
2 Press t#e D 1e$. 2#e file is re!ove fro! t#e pro@ect.
Sain+ proAects" )esi+ns" an) li*raries
E#en t#e pro@ect !anager 4ino4 is active, 4e can save a ne4 or eCisting pro@ect,
esign, or librar$. 2#e Save co!!an saves all open ocu!ents reference b$ t#e
pro@ect, as 4ell as t#e pro@ect itself.
2#e Save As co!!an saves files epening on 4#at 4e #ave selecte in t#e pro@ect
!anager.
" (f one or !ore esigns or libraries are selecte, 4e are pro!pte to save eac# file in
turn.
"(f no top"level folers )Design 6esources or Outputs* are selecte, an ite!s ot#er
t#an
Designs or libraries are selecte, t#e Save As co!!an is unavailable.
"(f no esigns or libraries are selecte in t#e pro@ect !anager, $ou are pro!pte
to save t#e pro@ect.
To sae a ne; )esi+n or li*rar!
Eit# t#e esign or librar$ selecte in t#e pro@ect !anager, fro! t#e 5ile !enu,
c#oose Save. 2#e Save As ialog boC ispla$s.
<nter a na!e for t#e esign or librar$ in t#e 5ile na!e teCt boC, specif$ a
location, t#en c#oose t#e Save button.
2#e esign or librar$ is save, an t#e pro@ect !anager re!ains open. E#en 4e
close t#e pro@ect, Capture pro!pts 4e to save t#e pro@ect file.
To sae an existin+ proAect
1
Eit# t#e Design 6esources or Output foler selecte, c#oose Save fro! t#e 5ile
!enu.
2#e pro@ect is save, an re!ains open in t#e Capture session fra!e.
C$OSIN( % P&OCECT
To close a proAect
5ro! t#e pro@ect !anagerDs 5ile !enu, c#oose
Close Pro@ect. E#en 4e close a pro@ect, a
ialog boC ispla$s, as1ing if 4e 4ant to save
c#anges.
To Duit Capture
5ro! t#e pro@ect !anagerDs 5ile !enu, c#oose <Cit.
C#oose Wes to save t#e specific ocu!ent
C#oose Wes All to save all ocu!ents in t#e pro@ect.
C#oose =o to close t#e ocu!ent 4it#out saving it.
C#oose =o All to close all open ocu!ents 4it#out saving t#e!.
C#oose Cancel to abort closing t#e pro@ect.
SETTIN( UP P&OCECT
Capture provies ifferent levels of configuration. 3sing co!!ans on t#e Options
!enu, 4e can9
Custo!ize t#e 4or1ing environ!ent specific to our s$ste! )using Preferences*.
Create efault settings for ne4 esigns )using Design 2e!plate*. 2#ese settings sta$
4it# t#e esign as esign properties even if it is !ove to anot#er s$ste! 4it#
ifferent preferences.
Overrie settings in iniviual esigns )using Design Properties* or iniviual
sc#e!atic pages )using Sc#e!atic Page Properties*.
6egarless of 4#ic# Capture 4ino4 is active, t#e Options !enu #as a
Preferences co!!an an a Design 2e!plate co!!an. (n aition, t#e Options
!enu contains co!!ans specific to t#e current active 4ino4. 5or eCa!ple, t#e
pro@ect !anagerDs Options !enu contains t#e Design Properties co!!an, 4#ile t#e
sc#e!atic page eitorDs Options !enu contains t#e sc#e!atics page properties
co!!an.
2#e settings in t#e Preferences ialog boC eter!ine #o4 Capture 4or1s on our s$ste!,
an persist fro! one Capture session to t#e neCt because t#e$ are store in t#e Capture
initialization ).(=(* file on our s$ste!. (f 4e pass pro@ects to ot#ers, t#e$ 4onDt
in#erit our Preferences settings. 2#is !eans 4e can set colors, gri ispla$ options, pan
1
an zoo! options, an so on to our li1ing an be assure t#at our settings 4ill re!ain,
even if 4e 4or1 on a pro@ect create on anot#er s$ste!.
2#e Design 2e!plate ialog boC eter!ines t#e efault c#aracteristics of all t#e pro@ects
create on our s$ste!. Because a ne4 pro@ect in#erits c#aracteristics fro! t#e current
Design 2e!plate settings, itDs a goo iea to c#ec1 t#e settings before 4e create a ne4
pro@ect.
Once 4e begin 4or1ing on a pro@ect, 4e can custo!ize its particular c#aracteristics
b$ c#oosing Design Properties fro! t#e Options !enu 4#en 4e are in t#e pro@ect
!anager or Sc#e!atic Page Properties 4#en 4e are in t#e sc#e!atic page eitor.
DE<ININ( SE$ECTION OPTIONS
4e can specif$ 4#et#er ob@ects are selecte 4#en t#e selection borer intersects t#e!
or if t#e ob@ects are selecte onl$ 4#en t#e$ are co!pletel$ enclose in t#e selection
area. 4e can also c#ange t#e !aCi!u! nu!ber of ob@ects ispla$e at #ig# resolution
4#ile ragging, an set tool palette visibilit$ in bot# t#e sc#e!atic page eitor, an t#e
part an s$!bol eitor.
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Select ta* of the Preferences )ialo+ *ox
To )efine selection options
5ro! t#e Options !enu, c#oose Preferences, t#en c#oose t#e Select tab.
5or t#e sc#e!atic page eitor an t#e part eitor, set t#ese options9
%rea Select. Specif$ 4#et#er to select ob@ects t#at are insie an
(ntersecting t#e selection borer or onl$ ob@ects t#at are full$ enclose b$ t#e
selection borer.
Maximum num*er of o*Aects to )ispla! at hi+h resolution ;hile
)ra++in+. (f 4e rag !ore ob@ects t#en 4e specif$ #ere, 4e 4ill see
rectangular place#olers for t#e ob@ects as 4e rag t#e!.
Sho; Palette. Select t#is c#ec1 boC to !a1e t#e tool palette visibleI
eselect it to !a1e t#e tool palette invisible. Clic1 O>.
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Settin+ miscellaneous options
4e can specif$ t#e efault fill, line st$le an 4it#, an color for grap#ics ob@ects,
efine t#e font use in t#e pro@ect !anager an session log, rener 2rue2$pe fonts
4it# stro1es )for printing an plotting*, an set 4#et#er to enable auto recover$ for our
pro@ect an #o4 often. (n aition, 4e can enable intertool co!!unication, 4#ic# is
t#e !et#o t#at Capture uses to co!!unicate 4it# ot#er OrCAD soft4are, suc# as
OrCAD <Cpress, OrCAD PSpice, an OrCAD %a$out.
Miscellaneous ta* of the Preferences )ialo+ *ox
To set miscellaneous options
1 5ro! t#e Options !enu, c#oose Preferences, t#en c#oose t#e Miscellaneous tab.
2 5or t#e sc#e!atic page eitor an t#e part eitor, set t#ese options9
<ill St!le. Select t#e fill pattern to be use 4#en ra4ing rectangles, ellipses, an
close s#apes ra4n 4it# t#e pol$line tool.
$ine St!le an) 'i)th. Select t#e line st$le an 4it# use for lines, pol$lines,
rectangles, ellipses.
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<or the schematic pa+e e)itor" set this option=
Color. Select t#e color use for grap#ic ob@ect )rectangles, ellipses, an close
pol$lines*.
Set the follo;in+ options=
ProAect Mana+er an) Session $o+.
Select a font for ispla$ teCt in t#e pro@ect !anager an session log. (f 4e select t#is
option, a stanar Eino4s ialog boC for font selection appears. Select a font, st$le, an
size fro! t#e ialog boC, t#en clic1 O>.
Text &en)erin+.
2#e teCt renering options affect #o4 teCt on a sc#e!atic page appears on $our
screen, an #o4 it is printe or plotte. 2#e 6ener 2rue2$pe fonts 4it# stro1es
option ispla$s teCt as a series of lines, connecte to rese!ble t#e outlines of t#e
corresponing 2rue2$pe letters or nu!bers t#e$ represent. <nabling t#e 5ill teCt
option causes t#e teCt outlines to be fille in.
%uto &ecoer!.
Select 4#et#er to enable auto recover$ for our pro@ect an, if so, t#e interval
bet4een saves. 4e can specif$ an$ interval bet4een five !inutes an 120 !inutes.
E#en t#e ti!e interval is up, an$ esign, librar$, or ;&D% file in $our pro@ect t#at
#asnDt been save, or #as been !oifie since t#e last save, is save as a te!porar$
file )4it# an .ASP eCtension* in t#e E(=DOESK 2<MPK A32OSA;< irector$.
E#en 4e close our pro@ect nor!all$, t#e K A32OSA;< irector$ an te!porar$
files are elete. (n cases of po4er outages or s$ste! cras#es, #o4ever, t#e
te!porar$ files are save. E#en 4e restart Capture, it loas t#e auto recovere files,
s#o4ing A6estoreB in t#eir title bars. 4e !ust use t#e Save As co!!an an
provie a filena!e to #ave an auto recovere file over4rite t#e original file.

%uto &eference.
Select 4#et#er to enable auto!atic annotating of reference esignators 4#en parts
are place.
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Intertool Communication. Select 4#et#er to enable intertool co!!unication
)also 1no4n as (2C*, so t#at $ou can test an ispla$ esign infor!ation using ot#er
OrCAD soft4are )suc# as %a$out, PSpice, an <Cpress* in con@unction 4it# Capture.
Capture processes its tools faster 4#en intertool co!!unication is not selecte.
Clic1 O>.
Settin+ text e)itor options
CaptureDs teCt eitor options inclue auto!atic #ig#lig#ting of ;&D% 1e$4ors,
co!!ents, or 7uote strings. Ee can also set t#e font, t#e tab spacing, an enable or
isable t#e #ig#lig#ting feature.
Text E)itor ta* of the Preferences )ialo+ *ox
1
To set text e)itor options
5ro! t#e Options !enu, c#oose Preferences, t#en c#oose t#e 2eCt <itor tab.
Set t#ese options9
S!ntax #i+hli+htin+. Select t#e color to use to #ig#lig#t ;&D% 1e$4ors,
co!!ents, an 7uote.
Current <ont Settin+. Clic1 Set to c#ange t#e font setting for t#e teCt eitor to values
ot#er t#an t#ose ispla$e.
Ta* Spacin+. Set t#e tab spacing for t#e teCt eitor.
C#ec1 t#e &ig#lig#t >e$4ors, Co!!ents, an [uote Strings option to #ave
t#ose ;&D% ite!s #ig#lig#te in t#e teCt eitor. 2#e colors use to #ig#lig#t
t#ese ite!s are t#e ones set in t#e S$ntaC &ig#lig#ting group boC.
(f 4e 4ant to reset t#e teCt eitor options to t#e Capture efault values, clic1 t#e 6eset
button.
Clic1 O>.
SETTIN( UP P&OCECT TEMP$%TES
2#e options t#at 4e efine in t#e Design 2e!plate ialog boC are t#e efault settings for
all ne4 pro@ects, an for sc#e!atic pages $ou a to an eCisting pro@ect. 4e can
overrie so!e of t#ese options for iniviual pro@ects or sc#e!atic pages. So!e of t#e
t#ings 4e can efine in t#e Design 2e!plate ialog boC are9
<onts. 4e can efine t#e fonts for sc#e!atic page ob@ects t#at contain teCt,
suc# as part references an values.
Title /lock. 4e can specif$ t#e teCt to appear in title bloc1 fiels, as 4ell as
t#e pat# an filena!e of t#e librar$ containing t#e title bloc1. 2#is affects
ne4 pro@ects, as 4ell as ne4 sc#e!atic pages in eCisting pro@ects.
Pa+e Si0e. 4e can specif$ 4#et#er inc#es or !illi!eters are use as t#e
unit of !easure, t#e 4it# an #eig#t of a sc#e!atic page, an t#e spacing
bet4een pins.
(ri) &eference. 5or #orizontal an vertical borer gri references, 4e can set
1
t#e nu!ber of borer gri references to ispla$ in eit#er irection, 4#et#er t#e
gri references are alp#abetic or nu!eric, 4#et#er t#e$ incre!ent or
ecre!ent across t#e sc#e!atic page, an #o4 4ie gri reference cells are.
Ee can also !a1e t#e borer, gri references, an title bloc1 visible or invisible.
2#is affects ne4 pro@ects, as 4ell as ne4 sc#e!atic pages in eCisting pro@ects.
#ierarch!. 5or #ierarc#ical bloc1s an part instances t#at #ave t#eir
Pri!itive propert$ set to Default, 4e can specif$ if 4e 4ant Capture to treat
eac# as pri!itive )cannot escen into attac#e sc#e!atic folers* or no
pri!itive )can escen into attac#e sc#e!atic folers*.
SDT Compati*ilit!. 4e can specif$ 4#ic# Capture properties !ap to 4#ic#
OrCAD Sc#e!atic Design 2ools )SD2* part fiels 4#en saving a pro@ect in
SD2 for!at.
Definin+ title *lock information
2#ere are t4o t$pes of title bloc1s9 efault an optional.
4e specif$ t#e infor!ation t#at goes into t#e efault title bloc1 in t#e 2itle Bloc1 tab
of t#e Design 2e!plate ialog boC. Capture places a efault title bloc1 in t#e lo4er rig#t
corner of eac# sc#e!atic page )if a librar$ an title bloc1 na!e are specifie*, an
places t#e infor!ation 4e enter in t#e teCt fiels in t#e 2itle Bloc1 tab into t#e title
bloc1. 2#is infor!ation is also use in reports create b$ t#e co!!ans on t#e 2ools
!enu. 2#is affects ne4 pro@ects, as 4ell as ne4 sc#e!atic pages in eCisting pro@ects.
4e can set t#e efault title bloc1 to be visible or invisible on an eCisting sc#e!atic
page b$ c#anging t#e setting in t#e 8ri 6eferences tab in t#e Sc#e!atic Page Properties
ialog boC.
4e can place an$ nu!ber of optional title bloc1s an$4#ere on t#e sc#e!atic page
using t#e 2itle Bloc1 co!!an on t#e Place !enu. Optional title bloc1s ispla$
infor!ation t#at $ou efine as propert$ values for t#e title bloc1 s$!bol.
1
Title /lock ta* of the Desi+n Template )ialo+ *ox
Capture provies efault title bloc1 s$!bols in t#e CAPSWM.O%B librar$. One suc#
title bloc1 is s#o4n belo4. 2#e teCt s#o4n in curl$ braces acts as propert$ teCt
place#olers. 4e can specif$ t#e value b$ ouble"clic1ing on t#e teCt an suppl$ing
a value. 4e can control t#e visibilit$ b$ selecting or eselecting t#e ;isible c#ec1 boC
in t#e Displa$ Properties ialog boC.
Title *lock
1
To choose a title *lock an) )efine the text it contains
1 5ro! t#e Options !enu, c#oose Design 2e!plate, t#en c#oose t#e 2itle Bloc1 tab.
2 (n t#e 2eCt group boC, enter t#e infor!ation 4e 4ant to appear in t#e title bloc1.
3 (n t#e S$!bol group boC, enter t#e pat# an filena!e of t#e librar$ containing t#e
title bloc1.
2#e %ibrar$ =a!e teCt boC can be left blan1 if $ou are using title bloc1
fro! t#e CAPSWM.O%B librar$ an CAPSWM.O%B #as not been !ove to
a ifferent irector$ fro! 4#ere it 4as installe.
(f 4eare using a custo! title bloc1, t#en put t#efull pat# an file na!e for
t#e librar$ in t#e %ibrar$ =a!e teCt boC.
' <nter t#e eCact na!e of t#e title bloc1 into t#e 2itle Bloc1 =a!e teCt boC. S$!bol
na!es are case sensitive an space sensitive.
+ Clic1 O>.
Settin+ the schematic pa+e si0e for ne; proAects
5or ne4 pro@ects, 4e can specif$ t#e efault unit of !easure, t#e efault 4it# an
#eig#t of sc#e!atic pages, an t#e spacing bet4een pins. 2#e value 4e enter in t#e Pin"
to"Pin Spacing teCt boC efines #o4 close toget#er pins are place in t#e part eitor. (t
also efines t#e gri spacing )t#e space bet4een gri ots or gri lines*
Pa+e Si0e ta* of the Desi+n Template )ialo+ *ox
1
To set up the schematic pa+e si0e
1 5ro! t#e Options !enu, c#oose Design 2e!plate, t#en c#oose t#e Page Size tab.
2 (n t#e 3nits area, select t#e efault unit of !easure for ne4 pro@ects. 2#is setting
onl$ affects t#e sc#e!atic page eitor, not t#e part eitor.
3 Select t#e efault sc#e!atic page size for ne4 pro@ects. 5or eac# sc#e!atic page
size )A, B, C, D, <, an Custo! if t#e unit of !easure is (nc#esI or A', A3, A2, A1,
A0, an Custo! if t#e unit of !easure is Milli!eters* $ou can specif$ t#e 4it# an
#eig#t. 2#e values t#at $ou enter in t#e Eit# an &eig#t teCt boCes beco!e t#e
i!ensions for eac# page size. Wou cannot c#ange t#ese i!ensions for iniviual
sc#e!atic pages, alt#oug# $ou can select a ifferent page size, or c#oose to efine a
custo! size.
' (n t#e Pin"to"Pin Spacing teCt boC, specif$ t#e efault spacing bet4een pins. 2#e
value $ou enter in t#is teCt boC efines #o4 close toget#er pins are 4#en $ou place a
part on a sc#e!atic page. (t also efines t#e gri spacing )t#e space bet4een gri
ots or gri lines*. Wou cannot c#ange t#is value for eCisting pro@ects or iniviual
sc#e!atic pages.
Definin+ the +ri) reference
4e set t#e borerDs gri references to ispla$ eit#er #orizontall$ or verticall$,
alp#abeticall$ or nu!ericall$, incre!entall$ or ecre!entall$ across t#e sc#e!atic page,
an t#e 4it# of t#eir cells. Wou can also !a1e t#e borer, gri references, an title bloc1
visible or invisible on t#e screen an on sc#e!atic pages $ou print. 2#e settings affect
ne4 pro@ects an ne4 sc#e!atic pages in eCisting pro@ects.
1
(ri) &eference ta* of the Desi+n Template )ialo+
To )efine the +ri) reference
1 5ro! t#e Options !enu, c#oose Design 2e!plate, t#en c#oose t#e 8ri 6eference tab.
2Specif$ t#e nu!ber of borer gri references, 4#et#er t#e$ are alp#abetic or nu!eric,
4#et#er t#e gri references incre!ent )Ascening* or ecre!ent )Descening* across
t#e sc#e!atic page, an #o4 4ie t#e gri reference cells are.
35or t#e borer, title bloc1, an gri reference, selects Displa$e to #ave t#e ite! ispla$ on
screen or Printe to #ave t#e ite! appear on sc#e!atic pages $ou print..
1
$%@OUT
E#at is %a$outZ
%a$out is one part for t#e PCB Design in 4#ic# 4e place as 4ell as route t#e co!ponents an set
unit of !easure!ents, gris, an spacing in orca. Eit# ot#er soft4ares $ou also #ave to place
an route t#e co!ponents in a si!ilar 4a$. 5or t#e place!ent an routing of t#e co!ponents 4e
nor!all$ use Auto"place!ent an Auto"routing.
6epetition of t#e steps for boar esign 9"
At first, 4e #ave create a netlist fro! our sc#e!atic iagra! b$ using capture.
%a$out inclues esign rules in orer to guie logical place!ent an routing.
2#at !eans, loa t#e netlist into la$out to create t#e boar. At t#e sa!e ti!e $ou #ave to
specif$ t#e boar para!eters.
Specif$ boar para!eters9" Specif$ global setting for t#e boar, incluing units of
!easure!ents, grie an spacing. (n aition , $ou create boar outline an efine t#e
la$erstac1s, pastac1s, an vias.
Place co!ponents9" 3se t#e co!ponent tool in orer to place !anuall$ t#e
co!ponents 4#ic# are fiCe b$ t#e s$ste! esigner on $#r boar or ot#er4ise Auto"
place!ent.
6oute t#e boar9" 3se ifferent routing tec#nologies to route t#e boar an ta1e
avantage of pus# an s#ove, in 4#ic# !oves t#e trac1s to !a1e roo! for t#r trac1
$ou are currentl$ routing as 4ell as $ou can also auto route t#e boar.
Provie finis#ing of t#e boar9" la$out supplies an orere progression of co!!ans
on t#e Auto !enu for finis#ing $our esign. 2#ese co!!ans inclues Design 6ule
C#ec1, clean up esign, 6ena!e co!ponents, bac1 Annotate, 6un post processor, an
create reports.
67
The Desi+n 'in)o;=
T#e esign 4ino4 provies a grap#ical ispla$ of printe circuit boar, it is a pri!ar$ 4ino4
$ou use 4#en esign $our boar. (t also provies tools to facilitate t#e esign process suc# as to
upate co!ponents an esign rules violations. 2#e esign 4ino4 appears 4#en $ou open a ne4
eCisting boar.
The $i*rar! Mana+er
2#e %ibrar$ Manager Eino4 is use to vie4, eit an create footprints an footprints libraries.
4e can assign footprints to co!ponents in boar. 4e can also !oif$ an c#ange footprints pa
stac1s in t#e librar$ !anager. 2#e librar$ !anager is split into t4o 4ino4s one is librar$
!anager an secon is footprint 4ino4.
68
To open the li*rar! mana+er
C#oose t#e librar$ !anager toolbar button or fro! t#e file !enu, c#oose t#e librar$ !anager.
The session lo+
2#e session log lists all t#e events t#at #ave occurre relate to t#e currentl$ open boar. (f 4e are
facing an$ proble!s uring esigning la$out t#en 4e can see all t#e errors in t#e session log an
verif$ our esign errors.
2o open t#e session log9
5ro! t#e file !enu, c#oose teCt eitor appears li1e a notepa.
5ro! t#e teCt eitorDs file !enu, c#oose open. 2#e open ialog boC appears.
The tool*ar
B$ c#oosing a tool in t#e toolbar, 4e can 7uic1l$ perfor! t#e !ost fre7uent la$out tas1s. E#en
4e !ove t#e pointer over a toolbar button, t#e buttonDs na!e appears belo4 t#e button.
69
70
71
72
Metho) to create a *oar) ;ith $a!out Plus=
<nsure t#at net list 4it# all footprints an necessar$ infor!ation #as been create.
Create a irector$ in 4#ic# t#e sc#e!atic esign, net list, an boar 4ill co"eCit an put t#e
sc#e!atic esign an net list. OrCa provies a irector$ for t#is purpose.
5ro! t#e la$out session fra!eDs file !enu, c#oose =e4. 2#e loa te!plate file in t#e ialog boC
ispla$e.
Desi+n ;in)o;
73
Select t#e tec#nolog$ te!plate ).2C&*, t#en c#oose t#e open button an loa t#e net list in ot#er
boC.
2#en appl$ t#e auto <CO.
(f necessar$, respon to lin1 footprints to co!ponent ialog.
Dra4 t#e boar outline b$ using t#e obstacle tool in t#e tool bar.
Settin+ *oar) parameters=
2#ere is so!e para!eter 4#ic# s#oul be set before placing t#e co!ponents on boar. 2#e$ are
as follo4s9"
Set Datu!
Create a boar outline
Set units of !easure!ents
Set s$ste! gri
A !ount #oles

Creatin+ of *oar) outline=
Boar outline is t#e grap#ical representation of t#e size of t#e actual PCB boar. So it is t#e !ain
step in la$out, to ra4 t#e boar outline of t#e actual size of PCB boar.

74
Placement of components=
Place!ent of co!ponents !eans t#at to place t#e co!ponents in esigne boC. A esigner s#oul
follo4 t#e follo4ing steps before going for it9"
Opti!ize t#e boar for co!ponent place!ent.
%oa t#e place!ent strateg$ file.
Place co!ponents on t#e boar.
Opti!ize place!ent using various place!ents
Co!ponents can be place b$ using t4o tec#ni7ues9"
1* Manual place!ent of co!ponents
2* Auto place!ent of co!ponents
C#oose t#e co!ponents tool bar button. 5ro! t#e pop up !en, c#oose t#e 7ueue for place!ent.
2#e co!ponents selection criteria ialog boC appears. <nter t#e reference esignator of t#e
co!ponents t#at 4e 4ant to place in t#e appropriate teCt boC, an clic1 o1. Drag t#e co!ponents
to esire location, place it t#ere.
75
Con)uctor &outin+ in $a!out=2
After placing all t#e co!ponents t#e ot#er !ain step is to route t#e boar fro! t#e electrical
connections bet4een t#e co!ponents. One !a$ route boar !anuall$ or auto!aticall$ b$ auto
router.
100L auto routing can be ac#ieve onl$ 4#en co!ponents are place in t#e orer of functional
flo4 of electronic circuit. 2#e !ain routing tool available in OrCa is as flo49"
AKeit route !oe
<it seg!ent !oe
S#ove trac1 !oe
Auto pat# route !oe
Desi+n &ule Check=2
(n !anual esigns ever$ t#ing 4as c#ec1e as a possible source of error. Co!ponents sizes, #ole
sizes, conuctor 4it#s an clearance, lan"to"#ole"ratio, boar areas to be free of co!ponents,
clearance to t#e eges, positional accurac$ an of course electrical interconnections #a ta to be
personall$ revie4e 4it# a great eal of care. After co!pleting t#e esign of printe circuit boar
4it# t#e #elp of an <DA"2ool, a esigner #as again to verif$ t#e PCB in orer to fin out errors.
Suc# t$pe of verificationsKesign rule c#ec1 contains besie t#e general verifications co!!onl$
t4o t$pes9"
P#$sical verification
<lectrical verification
76
Post processin+=2
Post processing can be one once t#e esign is co!plete in all aspects. 2#e co!!on 4a$ is still
a process to generate 8<6B<6 ata an =CD files 4#ic# can be use for p#oto plotting an for
steps of C=C !anufacturing an PCB" rilling.
PO'E& S@STEM DESI(N
5irst part of electronics c1ts. is po4er. 2#e !ain po4er suppl$ is in AC but !ostl$ electronic c1ts.
4or1 4it# DC. So a s$ste! is re7uire to convert ac to c an t#ese sources s#oul able to
prouce stable supplies. Po4er supplies !a$ be use in. !a$ be of ifferent t$pes suc# as
regulate, unregulate, s!ps etc.
Unre+ulate) po;er supplies
2#ese are t#e po4er supplies in 4#ic# t#e out put is not constant. 2#at it is varies 4it# input
voltage, loa, an also effecte b$ t#e environ!ent conitions suc# as te!perature, etc. so
t#ese are t#e variable supplies. Co!!onl$ t#ese supplies are not e!plo$e as t#ere efficienc$
is ver$ less. 2#e unregulate po4er can be obtaine using rectif$ing circuit after AC suppl$.
&e+ulate) po;er supplies
2#ese are t#e po4er supplies in 4#ic# t#e output voltage is constant, i.e. t#e out put voltage
is inepenent of t#e input voltage, loa an ot#er eCternal conitions. So to obtain t#e
regulate voltage using ifferent regulators. 2#e regulator voltage is !ainl$ t#e DC voltage, it
!a$ AC to or DC to DC voltage. A better approac# to po4er suppl$ esign is to use enoug#
capacitance to reuce ripple to lo4 level, t#en use an active feebac1 circuit to eli!inate t#e
re!aining ripple an epenence of output voltage on input, loa an environ!ent conitions.
77
2#ese active evices are 1no4n as 6egulators. 2#ese regulators can be use to prouce
negative an positive voltage of re7uire value.
2#e voltage regulators are of t#ree t$pes9"
1* Constant positive voltage regulators
2* Constant negative voltage regulators
3* ;ariable voltage regulators
Constant positie olta+e re+ulators=2
2#ese are t#e regulators 4#ic# are able to prouce positive an constant voltage. So!e of t#e!
are given belo49"
S. no. =a!e of regulator Output voltage
1 %M -.0+ +v
2 %M -.10 10v
3 %M -.12 12v
' %M -.1+ 1+v
2#ese regulators are use accoring to t#e re7uire voltage nee.
Constant ne+atie olta+e re+ulators=2
2#ese are also t#e constant output voltage regulator but t#ere output is negative in polarit$. 2#ese
regulators are also e!plo$e accoring to voltage re7uire!ents. So!e of t#e! are given belo4
4it# t#ere outputs9"
S. no =a!e of regulator Output voltage
1 %M-/0+ "+v
2 %M-/10 "10v
3 %M-/12 "12v
' %M-/1+ "1+v
78
?aria*le olta+e re+ulators=2
2#ese are t#e regulator 4#ose output voltage can be varie accoring to t#e esire nee. 2#ese
regulators again of t4o t$pes i.e.9"
Positive
=egative
2#e output of t#ese regulators can be varie b$ var$ing t#e resistance of t#e variable resistance
4#ic# is connecte to t#e a@ustable pin t#e regulators. So t#ese are t#e !ost co!!onl$ use
regulators in t#e electronic inustr$ as 4ie range of stable voltage can be obtaine fro! single
c#ip b$ var$ing t#e resistance connecte to t#e a@ustable pin of t#e regulators. 2#e !ost
co!!onl$ variable regulators are9"
%M31- )it is positive regulator*
%M 33-)it is negative regulator*
79
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