R5F102AA
R5F102AA
R5F102AA
RL78/G12
R01DS0193EJ0200
Rev.2.00
Sep 06, 2013
RENESAS MCU
True Low Power Platform (as low as 63 A/MHz), 1.8V to 5.5V operation,
2 to 16 Kbyte Flash, 31 DMIPS at 24MHz, for General Purpose Applications
1. OUTLINE
<R>
1.1 Features
Ultra-Low Power Technology
1.8 V to 5.5 V operation from a single supply
Stop (RAM retained): 0.23 A, (LVD enabled): 0.31 A
Snooze: 0.7 mA (UART), 1.20 mA (ADC)
Operating: 63 A /MHz
16-bit RL78 CPU Core
Delivers 31 DMIPS at maximum operating frequency
of 24 MHz
Instruction Execution: 86 % of instructions can be
executed in 1 to 2 clock cycles
CISC Architecture (Harvard) with 3-stage pipeline
Multiply Signed & Unsigned: 16 x 16 to 32-bit result in
1 clock cycle
MAC: 16 x 16 to 32-bit result in 2 clock cycles
16-bit barrel shifter for shift & rotate in 1 clock cycle
1-wire on-chip debug function
Main Flash Memory
Density: 2 KB to 16 KB
Block size: 1 KB
On-chip single voltage flash memory with protection
from block erase/writing
Data Flash Memory
Data Flash with background operation
Data flash size: 2 KB size options
Erase Cycles: 1 Million (typ.)
Erase/programming voltage: 1.8 V to 5.5 V
RAM
256 B to 1.5 KB size options
Supports operands or instructions
Back-up retention in all modes
High-speed Oscillator Oscillator
24MHz with +/- 1% accuracy over voltage (1.8 V to
5.5 V) and temperature (-20 C to 85 C)
Pre-configured settings: 24 MHz, 16 MHz, 12 MHz,
8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz
Reset and Supply Management
Power-on reset (POR) monitor/generator
Low voltage detection (LVD) with 12 setting options
(Interrupt and/or reset function)
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Sep 06, 2013
Page 1 of 106
RL78/G12
1. OUTLINE
Data flash
RAM
20 pins
24 pins
30 pins
16 KB
2 KB
2 KB
R5F102AA
2 KB
1.5 KB
12 KB
2KB
1 KB
8 KB
2 KB
768 B
4 KB
2KB
512 B
2 KB
2 KB
Notes 1.
256 B
R5F1026A
Note 1
R5F1036A
Note 1
R5F10269
Note 1
R5F10369
Note 1
R5F10268
Note 1
R5F10368
Note 1
R5F103AA
R5F1027A
Note 1
R5F1037A
Note 1
R5F10279
Note 1
R5F102A9
R5F10379
Note 1
R5F103A9
R5F10278
Note 1
R5F102A8
R5F10378
Note 1
R5F103A8
R5F10267
R5F10277
R5F102A7
R5F10367
R5F10377
R5F103A7
R5F10266
Note 2
R5F10366
Note 2
This is 640 bytes when the self-programming function or data flash function is used. (For details, see
CHAPTER 3 CPU ARCHITECTURE in the RL78/G12 Users Manual Hardware.)
2.
Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used
because each library is used. When using the library, refer to RL78 Family Flash Self Programming
Library Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual.
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Page 2 of 106
RL78/G12
1. OUTLINE
Package type:
SP : LSSOP, 0.65 mm pitch
NA : HWQFN, 0.50 mm pitch
ROM capacity:
6 :
7:
8:
9 :
A :
2 KB
4 KB
8 KB
12 KB
16 KB
Pin count:
6 : 20-pin
7 : 24-pin
A : 30-pin
RL78/G12 group
102Note 1
103Notes 1, 2
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
Notes 1.
For details about the differences between the R5F102 products and the R5F103 products of RL78/G12,
2.
Products only for "A: Consumer applications (TA = -40 to +85C)" and "D: Industrial applications (TA = -40 to
see 1.3 Differences between the R5F102 Products and the R5F103 Products.
+85C)"
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Sep 06, 2013
Page 3 of 106
RL78/G12
1. OUTLINE
Pin
count
20
pins
Package
20-pin plastic
LSSOP
(4.4 6.5 mm,
0.65 mm pitch)
Data flash
Mounted
Not mounted
24
pins
24-pin plastic
HWQFN
(4 4 mm, 0.5
mm pitch)
Mounted
Not mounted
30
pins
30-pin plastic
LSSOP
(7.62 mm
(300), 0.65 mm
pitch )
Mounted
Not mounted
Fields of
Application
Part Number
Note For fields of application, see Figure 1-1. Part Number, Memory Size, and Package of RL78/G12.
<R>
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 4 of 106
RL78/G12
1. OUTLINE
1.3 Differences between the R5F102 Products and the R5F103 Products
The following are differences between the R5F102 products and the R5F103 products.
Whether the data flash memory is mounted or not
High-speed on-chip oscillator oscillation frequency accuracy
Number of channels in serial interface
Whether the DMA function is mounted or not
Whether a part of the safety functions are mounted or not
Data Flash
R5F102 products
2KB
Not mounted
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Sep 06, 2013
Page 5 of 106
RL78/G12
1. OUTLINE
Condition
MIN
MAX
Unit
High-speed on-chip
oscillator oscillation
TA = -20 to +85 C
-1.0
+1.0
TA = -40 to -20 C
-1.5
+1.5
frequency accuracy
TA = +85 to +105 C
-2.0
+2.0
Condition
MIN
MAX
Unit
High-speed on-chip
TA = -40 to + 85 C
-5.0
+5.0
oscillator oscillation
frequency accuracy
20, 24 pin
30 pin product
product
Serial interface
UART
CSI
2
Simplified I C
DMA function
Safety function
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
R5F103 product
20, 24 pin
30 pin
product
product
1 channel
3 channels
1 channel
2 channels
3 channels
1 channel
2 channels
3 channels
None
2 channels
None
CRC operation
Yes
None
RAM guard
Yes
None
SFR guard
Yes
None
Page 6 of 106
RL78/G12
1. OUTLINE
P20/ANI0/AV REFP
P42/ANI21/SCK01Note/SCL01Note/TI03/TO03
P41/ANI22/SO01Note/SDA01Note/TI02/TO02/INTP1
P40/KR0/TOOL0
P125/KR1/SI01Note/RESET
P137/INTP0
P122/KR2/X2/EXCLK/(TI02)/(INTP2)
P121/KR3/X1/(TI03)/(INTP3)
VSS
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
P21/ANI1/AV REFM
P22/ANI2
P23/ANI3
P10/ANI16/PCLBUZ0/SCK00/SCL00Note
P11/ANI17/SI00/RxD0/SDA00 Note/TOOLRxD
P12/ANI18/SO00/TxD0/TOOLTxD
P13/ANI19/TI00/TO00/INTP2
P14/ANI20/TI01/TO01/INTP3
P61/KR5/SDAA0/(RxD0)
P60/KR4/SCLA0/(TxD0)
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Page 7 of 106
RL78/G12
1. OUTLINE
<R>
18 17 16 15 14 13
19
12
20
11
21
10
22
9
23
8
24
7
1 2 3 4 5 6
P61/KR5/SDAA00/(RxD0)
P60/KR4/SCLA0/(TxD0)
P03/KR9
P02/KR8/(SCK01)Note/(SCL01)Note
Note
Note
P01/KR7/(SO01) /(SDA01)
P00/KR6/(SI01)Note
P125/KR1/SI01Note/RESET
P137/INTP0
P122/KR2/X2/EXCLK/(TI02)/(INTP2)
P121/KR3/X1/(TI03)/(INTP3)
VSS
VDD
INDEX MARK
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 8 of 106
RL78/G12
1. OUTLINE
P20/ANI0/AVREFP
Note
P01/ANI16/TO00/RxD1
Note
P00/ANI17/TO00/TxD1
P120/ANI19
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P60/SCLA0
P61/SDAA0
P31/TI03/TO03/INTP4/PCLBUZ0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P21/ANI1/AVREFM
P22/ANI2
P23/ANI3
P147/ANI18
P10/SCK00/SCL00Note/(TI07/TO07)
P11/SI00/RxD0/TOOLRxD/SDA00Note/(TI06/TO06)
P12/SO00/TxD0/TOOLTxD/(TI05/TO05)
P13/TxD2Note/SO20Note/(SDAA0)Note/(TI04/TO04)
P14/RxD2Note/SI20Note/SDA20Note/(SCLA0)/(TI03/TO03)
P15/PCLBUZ1/SCK20Note/SCL20Note/(TI02/TO02)
P16/TI01/TO01/INTP5/(RxD0)
P17/TI02/TO02/(TxD0)
P50/INTP1/SI11Note
Note
Note
P51/INTP2/SO11 /SDA11
P30/INTP3/SCK11Note/SCL11Note
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Page 9 of 106
RL78/G12
1. OUTLINE
REGC:
Regulator Capacitance
Analog input
RESET:
Reset
RxD0 to RxD2:
Receive Data
AVREFP:
EXCLK:
SCK20:
SCL00, SCL01,
INTP0 to INTP5
ANI16 to ANI22:
AVREFM:
KR0 to KR9:
Key Return
P00 to P03:
Port 0
SDA20, SDAA0:
P10 to P17:
Port 1
P20 to P23:
Port 2
P30 to P31:
Port 3
SO20:
P40 to P42:
Port 4
TI00 to TI07:
Timer Input
P50, P51:
Port 5
TO00 to TO07:
Timer Output
P60, P61:
Port 6
TOOL0:
Port 12
TOOLRxD, TOOLTxD:
P137:
Port 13
P147:
Port 14
TxD0 to TxD2:
Transmit Data
PCLBUZ0, PCLBUZ1:
VDD:
Power supply
Buzzer Output
Device
VSS:
Ground
X1, X2:
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RL78/G12
1. OUTLINE
TAU0 (4ch)
TI00/TO00
ch00
TI01/TO01
ch01
TI02/TO02
ch02
TI03/TO03
ch03
PORT 1
P10 to P14
PORT 2
P20 to P23
PORT 4
P40 to P42
PORT 6
P60, P61
PORT 12
SAU0 (2ch)
RxD0
TxD0
UART0
Code flash: 16 KB
Note
Data flash: 2 KB
SCK00
SI00
SO00
CSI00
SCK01
SI01
SO01
CSI01
SCL00
SDA00
IIC00
Note
IIC01
Note
SCL01
SDA01
PORT 13
P137
Buzzer/clock
output control
Note
PCLBUZ0
Interrupt control
RL78
CPU
core
Key return
6ch
KR0 to KR5
Interrupt control
4ch
INTP0 to INTP3
Note
DMA
2ch
RAM
1.5 KB
Note
CRC
Window watchdog
timer
TOOL0
12-bit Intervaltimer
On-chip debug
BCD adjustment
IICA0
Low Speed
On-chip
oscillator
15 kHz
RESET
Clock Generator
+
Reset Generator
Main OSC
1 to 20 MHz
X1 X2/EXCLK
Power-on
reset/voltage
detector
VDD
High-Speed
on-chip oscillator
1 to 24 MHz
VSS
TOOL TOOL
TxD RxD
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Sep 06, 2013
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RL78/G12
1. OUTLINE
TAU0 (4ch)
TI00/TO00
ch00
TI01/TO01
ch01
TI02/TO02
ch02
TI03/TO03
ch03
Port 0
P00 to P03
Port 1
P10 to P14
Port 2
P20 to P23
Port 4
P40 to P42
Port 6
P60, P61
Port 12
SAU0 (2ch)
RxD0
TxD0
UART0
SCK00
SI00
SO00
CSI00
SCK01
SI01
SO01
Code flash: 16 KB
Data flash: 2 KBNote
P137
Port 13
Buzzer/clock
output control
Note
CSI01
SCL00
SDA00
IIC00
Note
SCL01
SDA01
IIC01
Note
PCLBUZ0
Interrupt control
RL78
CPU
core
Key return
10ch
10
Interrupt control
4ch
DMA
2ch
RAM
1.5 KB
On-chip debug
BCD adjustment
IICA0
SCLA0
SDAA0
Multiplier &
divider/
multiplyaccumulator
RESET
Clock Generator
+
Reset Generator
Main OSC
1to 20 MHz
X1 X2/EXCLK
Low Speed
On-chip
oscillator
15 KHz
10-bit
A/D converter
11ch
High-Speed
On-chip
oscillator
1 to 24 MHz
Poer-on
reset/voltage
detector
IICA0
VDD
INTP0 to INTP3
CRCNote
Window watchdog
timer
TOOL0
KR0 to KR9
Note
VSS
TOOL TOOL
TxD RxD
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RL78/G12
1. OUTLINE
TAU (8ch)
TI00
TO00
ch0
TI01/TO01
ch1
TI02/TO02
ch2
Port 0
P00, P01
TI03/TO03
ch3
Port 1
P10 to P17
(TI04/TO04)
ch4
Port 2
P20 to P23
(TI05/TO05)
ch5
Port 3
P30, P31
(TI06/TO06)
ch6
(TI07/TO07)
ch7
P40
Port 4
SAU0 (4ch)
RxD0
TxD0
RxD1
TxD1
SCK00
SI00
SO00
SCK11
SI11
SO11
Code flash: 16 KB
Data flash: 2 KBNote
Port 5
P50, P51
Port 6
P60, P61
Port 12
UART0
P120
Note
UART1
P121, P122
Interrupt control
CSI00
RL78
CPU
core
DMANote
2ch
Port 13
P137
Port 14
P147
Note
CSI11
SCL00
SDA00
IIC00
SCL11
SDA11
IIC11
RAM
2 KB
Note
Buzzer/clock
output control
Interrupt control
6ch
Note
PCLBUZ0, PCLBUZ1
INTP0 to INTP5
CRCNote
RESET
SAU0 (2ch)Note
RxD2
TxD2
UART2
SCK20
SI20
SO20
CSI20
SCL20
SDA20
IIC20
Clock Generator
+
Reset Generator
X1 X2/EXCLK
Window watchdog
timer
Low Speed
On-chip
oscillator
15 KHz
High-Speed
On-chip
oscillator
1 to 24 MHz
Poer-on
reset/voltage
detector
VDD
TOOL0
Main OSC
1 to 20 MHz
VSS
TOOL TOOL
TxD RxD
10-bit
A/D converter
8ch
ANI2, ANI3,
ANI16 to ANI19
ANI0/AVREFP
ANI1/AVREFM
On-chip debug
VOLTAGE
REGULATOR
REGC
BCD adjustment
Multiplier &
divider/
multiplyaccumulator
SCLA0
SDAA0
IICA0
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G12
Users Manual Hardware.
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Page 13 of 106
RL78/G12
1. OUTLINE
20-pin
R5F1026x
24-pin
R5F1036x
2 to 16 KB
R5F1027x
R5F1037x
2 KB
Note 1
512 B to 2KB
1 MB
X1, X2 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 5.5 V
system
clock
R5F103Ax
2 KB
512 B to 1.5 KB
Address space
High-speed system clock
R5F102Ax
4 to 16 KB
2 KB
256 B to 1.5 KB
Main
30-pin
High-speed on-chip
HS (High-speed main) mode : 1 to 24 MHz (VDD = 2.7 to 5.5 V), 1 to 16 MHz (VDD = 2.4 to 5.5 V),
oscillator clock
15 kHz (TYP)
General-purpose register
Instruction set
I/O port
Total
CMOS I/O
<R>
CMOS input
18
22
26
12
16
21
(6 V tolerance)
Timer
16-bit timer
4 channels
Watchdog timer
1 channel
1 channel
Timer output
4 channels
(PWM outputs: 3
Notes 1.
8 channels
8 channels
Note 3
(PWM outputs: 7
Note 3 Note 2
2.
3.
The number of PWM outputs varies depending on the setting of channels in use (the number of masters and
slaves). (See 6.9.3
Hardware.)
Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used
because each library is used. When using the library, refer to RL78 Family Flash Self Programming
Library Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual.
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Page 14 of 106
RL78/G12
1. OUTLINE
(2/2)
Item
20-pin
R5F1026x
24-pin
R5F1036x
R5F1027x
30-pin
R5F1037x
R5F102Ax
R5F103Ax
2
11 channels
8 channels
I C bus
1 channel
accumulator
DMA controller
Vectored interrupt
Internal
sources
External
2 channels
2 channels
2 channels
18
16
18
16
26
19
Key interrupt
6
10
Reset
Note
Power-on-reset:
1.51 V (TYP)
Power-down-reset:
1.50 V (TYP)
Provided
Note
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Page 15 of 106
RL78/G12
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Page 16 of 106
RL78/G12
Parameter
Supply Voltage
Symbols
Conditions
Ratings
VDD
VIREGC
REGC
Unit
0.5 to + 6.5
0.3 to +2.8
Input Voltage
VI1
VI2
Output Voltage
VO
VAI
IOH1
Note 3
0.3 to 6.5
0.3 to VDD + 0.3
and 0.3 to
Notes 3, 4
AVREF(+)+0.3
Note 3
Per pin
40
mA
170
mA
70
mA
100
mA
P20 to P23
0.5
mA
mA
IOH2
Per pin
Total of all pins
IOL1
Per pin
40
mA
170
mA
70
mA
100
mA
mA
mA
Note 5
Per pin
Total of all pins
P20 to P23
Operating ambient
temperature
TA
40 to +85
Storage temperature
Tstg
65 to +150
Notes 1.
2.
3.
4.
5.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
2. AVREF (+): + side reference voltage of the A/D converter.
3. VSS: Reference voltage
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Page 17 of 106
RL78/G12
Parameter
X1 clock oscillation
Note
frequency (fX)
<R>
Note
Resonator
Ceramic resonator /
crystal oscillator
Conditions
MIN.
TYP.
MAX.
1.0
20.0
1.0
8.0
Unit
MHz
Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution
time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
<R>
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the
X1 clock oscillation stabilization time using the oscillation stabilization time counter status register
(OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the
oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation
stabilization time with the resonator to be used.
Remark
When using the X1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G12 Users Manual
Hardware.
Oscillators
High-speed on-chip oscillator
clock frequency
Parameters
Conditions
MIN.
MAX.
Unit
24
MHz
TA = 20 to +85C
-1.0
+1.0
TA = 40 to 20C
-1.5
+1.5
-5.0
+5.0
fIH
TYP.
Notes 1, 2
R5F102 products
15
fIL
kHz
clock frequency
Low-speed on-chip oscillator
-15
+15
Notes 1.
High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of
HOCODIV register.
2.
This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.
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Page 18 of 106
RL78/G12
2.3 DC Characteristics
2.3.1 Pin characteristics
(TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Note 1
IOH1
(1/4)
Conditions
MIN.
TYP.
MAX.
Unit
10.0
mA
Note 2
30.0
mA
6.0
mA
4.5
mA
80.0
mA
18.0
mA
10.0
mA
100
mA
0.1
mA
0.4
mA
30-pin products:
Total of P00, P01, P40, P120
(When duty 70%
Note 3
, P10 to P14
30-pin products:
Total of P10 to P17, P30, P31,
P50, P51, P147
(When duty 70%
Note 3
)
Note 3
Notes 1.
value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an
output pin.
2.
<R>
3.
4.
Caution P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41 for 24-pin products, and P00, P10
to P15, P17, and P50 for 30-pin products do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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Page 19 of 106
RL78/G12
Symbol
Note 1
(2/4)
Conditions
MIN.
IOL1
Note 4
TYP.
MAX.
Unit
20.0
mA
Note 2
mA
Note 2
60.0
mA
9.0
mA
30-pin products:
1.8
mA
80.0
mA
27.0
mA
5.4
mA
140
mA
0.4
mA
1.6
mA
Note 3
Note 3
)
Note 3
Notes 1.
Value of current at which the device operation is guaranteed even if the current flows from an output pin to
the VSS pin.
<R>
2.
3.
The output current value under conditions where the duty factor 70%.
If duty factor > 70%: The output current value can be calculated with the following expression (where n
represents the duty factor as a percentage).
Total output current of pins = (IOL 0.7)/(n 0.01)
<Example> Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 0.7)/(80 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
4.
Remark
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 20 of 106
RL78/G12
Symbol
VIH1
(3/4)
Conditions
MIN.
TYP.
MAX.
Unit
0.8VDD
VDD
Note 2
, P10 to P14,
P40 to P42
30-pin products: P00, P01, P10 to P17, P30, P31,
P40, P50, P51, P120, P147
VIH2
2.2
VDD
2.0
VDD
1.5
VDD
0.7VDD
VDD
0.7VDD
6.0
0.8VDD
VDD
0.2VDD
0.8
0.5
0.32
0.3VDD
0.3VDD
0.2VDD
VIH3
P20 to P23
VIH4
P60, P61
Note 1
VIH5
VIL1
Note 2
, P10 to P14,
P40 to P42
30-pin products: P00, P01, P10 to P17, P30, P31,
P40, P50, P51, P120, P147
VIL2
VIL3
P20 to P23
VIL4
P60, P61
Note 1
VIL5
VOH1
Note 2
, P10 to P14,
P40 to P42
30-pin products:
IOH1 = 3.0 mA
VDD1.5
VDD0.7
VDD0.6
VDD0.5
VDD0.5
IOH1 = 10.0 mA
VOH2
Notes 1.
2.
P20 to P23
IOH2 = 100 A
Caution The maximum value of VIH of pins P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41
for 24-pin products, and P00, P10 to P15, P17, and P50 for 30-pin products is VDD even in N-ch opendrain mode.
High level is not output in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 21 of 106
RL78/G12
Symbol
VOL1
(4/4)
Conditions
MAX.
Unit
1.3
0.7
0.6
0.4
0.4
IOL2 = 400 A
0.4
2.0
0.4
0.4
0.4
10
VI = VSS
10
100
Note
, P10 to P14,
IOL1 = 20.0 mA
4.0 V VDD 5.5 V,
IOL1 = 8.5 mA
TYP.
P40 to P42
P10 to P17, P30, P31, P40,
MIN.
VOL2
P20 to P23
VOL3
P60, P61
IOL1 = 15.0 mA
4.0 V VDD 5.5 V,
IOL1 = 5.0 mA
2.7 V VDD 5.5 V,
IOL1 = 3.0 mA
1.8 V VDD 5.5 V,
IOL1 = 2.0 mA
Input leakage current,
ILIH1
VI = VDD
P122
high
ILIH2
P121, P122
(X1, X2/EXCLK)
clock input
When resonator
connected
ILIL1
low
ILIL2
P121, P122
(X1, X2/EXCLK)
When resonator
connected
On-chip pull-up
RU
resistance
10
20
Note
, P10 to P14,
Note
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 22 of 106
RL78/G12
Symbol
IDD1
Note 1
(1/2)
Conditions
Note 3
MIN.
Basic
1.5
Normal
VDD = 5.0 V
operation VDD = 3.0 V
3.3
5.0
3.3
5.0
VDD = 5.0 V
2.5
3.7
VDD = 3.0 V
2.5
3.7
VDD = 3.0 V
1.2
1.8
VDD = 2.0 V
1.2
1.8
2.8
4.4
Resonator connection
3.0
4.6
2.8
4.4
Resonator connection
3.0
4.6
1.8
2.6
Resonator connection
1.8
2.6
1.8
2.6
Resonator connection
1.8
2.6
1.1
1.7
Resonator connection
1.1
1.7
1.1
1.7
Resonator connection
1.1
1.7
fIH = 16 MHz
main) mode
Note 3
fIH = 8 MHz
Note 4
Note 2
Note4
VDD = 5.0 V
Note 2
fMX = 20 MHz
VDD = 3.0 V
Note 2
fMX = 10 MHz
VDD = 5.0 V
Note 2
fMX = 10 MHz
VDD = 3.0 V
Note 2
LS(Low-speed
main) mode
fMX = 8 MHz
Note 4
VDD = 3.0 V
Note 2
fMX = 8 MHz
VDD = 2.0 V
<R>
Notes 1.
MAX.
VDD = 5.0 V
operation VDD = 3.0 V
Note 3
LS(Low-speed
TYP.
1.5
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
<R>
2.
3.
4.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS(Low speed main) mode:
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 23 of 106
RL78/G12
Symbol
IDD2
(2/2)
Conditions
Note 2
Note 1
HALT
HS (High-speed
mode
main) mode
fIH = 16 MHz
Note 4
fIH = 8 MHz
Note 4
Note 6
HS (High-speed
main) mode
fIH = 24 MHz
Note 6
LS (Low-speed
main) mode
MIN.
Note 4
Note 6
fMX = 20 MHz
Note 3
VDD = 5.0 V
fMX = 20 MHz
Note 3
VDD = 3.0 V
fMX = 10 MHz
Note 3
VDD = 5.0 V
fMX = 10 MHz
Note 3
VDD = 3.0 V
LS (Low-speed
main) mode
Note 6
fMX = 8 MHz
Note 3
VDD = 3.0 V
fMX = 8 MHz
Note 3
VDD = 2.0 V
IDD3
<R>
Notes 1.
Note 5
TYP.
MAX.
Unit
VDD = 5.0 V
440
1210
VDD = 3.0 V
440
1210
VDD = 5.0 V
400
950
VDD = 3.0 V
400
950
VDD = 3.0 V
270
542
VDD = 2.0 V
270
542
280
1000
Resonator connection
450
1170
280
1000
Resonator connection
450
1170
190
590
Resonator connection
260
660
190
590
Resonator connection
260
660
110
360
Resonator connection
150
416
110
360
Resonator connection
150
416
STOP
TA = 40C
0.19
0.50
mode
TA = +25C
0.24
0.50
TA = +50C
0.32
0.80
TA = +70C
0.48
1.20
TA = +85C
0.74
2.20
A
A
A
A
A
A
A
A
A
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
<R>
2.
3.
4.
5.
Not including the current flowing into the 12-bit interval timer and watchdog timer.
6.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS(Low speed main) mode:
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 24 of 106
RL78/G12
Symbol
(1/2)
Conditions
Operating HS (High-speed
IDD1
Note 1
mode
main) mode
MIN.
Note 3
Basic
fIH = 24 MHz
Note 4
VDD = 5.0 V
1.5
1.5
Normal
3.7
5.5
3.7
5.5
VDD = 5.0 V
2.7
4.0
VDD = 3.0 V
2.7
4.0
VDD = 3.0 V
1.2
1.8
VDD = 2.0 V
1.2
1.8
3.0
4.6
Resonator connection
3.2
4.8
3.0
4.6
Resonator connection
3.2
4.8
1.9
2.7
Resonator connection
1.9
2.7
1.9
2.7
Resonator connection
1.9
2.7
1.1
1.7
Resonator connection
1.1
1.7
1.1
1.7
Resonator connection
1.1
1.7
fIH = 8 MHz
Note 4
HS (High-speed
main) mode
Note 3
Note 4
Note 2
fMX = 20 MHz
VDD = 5.0 V
Note 2
fMX = 20 MHz
VDD = 3.0 V
Note 2
fMX = 10 MHz
VDD = 5.0 V
Note 2
fMX = 10 MHz
VDD = 3.0 V
LS (Low-speed
main) mode
Note 4
Note 2
fMX = 8 MHz
VDD = 3.0 V
Note 2
fMX = 8 MHz
VDD = 2.0 V
<R>
Notes 1.
Unit
mA
VDD = 5.0 V
Note 3
main) mode
MAX.
LS (Low-speed
TYP.
mA
mA
mA
mA
mA
mA
mA
mA
mA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
<R>
2.
3.
4.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS(Low speed main) mode:
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 25 of 106
RL78/G12
Symbol
IDD2
(2/2)
Conditions
Note 2
Note 1
HALT
HS (High-speed
mode
main) mode
fIH = 16 MHz
Note 4
fIH = 8 MHz
Note 4
Note 6
HS (High-speed
main) mode
fIH = 24 MHz
Note 6
LS (Low-speed
main) mode
MIN.
Note 4
Note 6
fMX = 20 MHz
Note 3
VDD = 5.0 V
fMX = 20 MHz
Note 3
VDD = 3.0 V
fMX = 10 MHz
Note 3
VDD = 5.0 V
fMX = 10 MHz
Note 3
VDD = 3.0 V
LS (Low-speed
main) mode
Note 6
fMX = 8 MHz
Note 3
VDD = 3.0 V
fMX = 8 MHz
Note 3
VDD = 2.0 V
I
<R>
Notes 1.
Note 5
DD3
TYP.
MAX.
Unit
VDD = 5.0 V
440
1280
VDD = 3.0 V
440
1280
VDD = 5.0 V
400
1000
VDD = 3.0 V
400
1000
VDD = 3.0 V
260
530
VDD = 2.0 V
260
530
280
1000
Resonator connection
450
1170
280
1000
Resonator connection
450
1170
190
600
Resonator connection
260
670
190
600
Resonator connection
260
670
95
330
Resonator connection
145
380
95
330
Resonator connection
145
380
STOP
TA = 40C
0.18
0.50
mode
TA = +25C
0.23
0.50
TA = +50C
0.30
1.10
TA = +70C
0.46
1.90
TA = +85C
0.75
3.30
A
A
A
A
A
A
A
A
A
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
<R>
2.
3.
4.
5.
Not including the current flowing into the 12-bit interval timer and watchdog timer.
6.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS (Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 26 of 106
RL78/G12
Symbol
IFIL
Conditions
MIN.
Note 1
TYP.
MAX.
Unit
0.20
0.02
0.22
onchip oscillator
operating current
12-bit interval
ITMKA
timer operating
Notes 1, 2, 3
current
Watchdog timer
IWDT
operating current
Notes 1, 2, 4
A/D converter
operating current
IADC
fIL = 15 kHz
Notes 1, 5
When conversion at
maximum speed
1.30
1.70
mA
0.50
0.70
mA
75.0
Note 1
75.0
A/D converter
IADREF
reference voltage
operating current
Note 1
Temperature
sensor operating
current
ITMPS
LVD operating
ILVD
Notes 1, 6
0.08
IFSP
Notes 1, 8
2.00
12.20
mA
Notes 1, 7
2.00
12.20
mA
0.50
0.60
mA
1.20
1.44
mA
0.70
0.84
mA
current
Selfprogramming
operating current
BGO operating
IBGO
current
SNOOZE
ISNOZ
Note 1
ADC operation
operating current
Note 9
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 27 of 106
RL78/G12
2.4 AC Characteristics
(TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V)
<R>
Items
Instruction cycle (minimum
Symbol
TCY
Conditions
MIN.
TYP.
MAX.
Unit
Main system
HS (High-
0.04167
clock (fMAIN)
speed main)
operation
mode
0.0625
0.125
LS (Lowspeed main)
mode
During self
HS (High-
0.04167
programming
speed main)
0.0625
0.125
1.0
20.0
MHz
1.0
16.0
MHz
1.0
8.0
MHz
24
ns
30
ns
60
ns
1/fMCK +
ns
mode
LS (Lowspeed main)
mode
External main system clock
fEX
frequency
tEXH, tEXL
tTIH, tTIL
10
fTO
frequency
PCLBUZ0, or PCLBUZ1
fPCL
output frequency
12
MHz
MHz
MHz
16
MHz
MHz
MHz
tKR
250
ns
tRSL
10
tINTH, tINTL
Remark
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 28 of 106
RL78/G12
<R> Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
10
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.1
0.0625
0.04167
0.01
0
1.0
2.0
3.0
2.4 2.7
4.0
5.0
5.5
6.0
10
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.125
0.1
0.01
0
1.0
2.0
1.8
3.0
4.0
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 29 of 106
RL78/G12
VIH/VOH
Test points
VIL/VOL
VIL/VOL
tEXH
EXCLK
TI/TO Timing
tTIH
tTIL
TI00 to TI07
1/fTO
TO00 to TO07
tINTL
INTP0 to INTP5
KR0 to KR9
RESET
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 30 of 106
RL78/G12
VIH/VOH
Test points
VIL/VOL
VIL/VOL
Symbol
Conditions
HS (high-speed
main) Mode
LS (low-speed
main) Mode
MIN.
MIN.
Transfer rate
Note 1
Notes 1.
<R>
2.
MAX.
Unit
MAX.
fMCK/6
fMCK/6
bps
4.0
1.3
Mbps
Note2
Caution
Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
Rx
TxDq
RL78
microcontroller
User's device
RxDq
Tx
TxDq
RxDq
Remarks 1.
2.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 31 of 106
RL78/G12
<R> (2) During communication at same potential (CSI mode) (master mode, SCK00... internal clock output,
corresponding CSI00 only)
Symbol
Conditions
HS (high-speed main)
LS (low-speed main)
Mode
Mode
MIN.
tKCY1
tKCY1 2/fCLK
SCK00 high-/low-
tKH1,
level width
tKL1
tSIK1
Note 1
MIN.
MAX.
83.3
250
ns
tKCY1/27
tKCY1/250
ns
tKCY1/210
tKCY1/250
ns
23
110
ns
33
110
ns
10
10
ns
tKSI1
(from SCK00)
MAX.
Unit
Note2
tKSO1
C = 20 pF
Note 4
10
10
ns
SCK00 to SO00
output
Note 3
Notes 1.
When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 setup time becomes to
SCK00 when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
2.
When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 hold time becomes from
SCK00 when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
3.
When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The delay time to SO00 output becomes
from SCK00 when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
4.
Caution Select the normal input buffer for the SI00 pin and the normal output mode for the SO00 and SCK00
pins by using port input mode register 1 (PIM1) and port output mode register 1 (POM1).
Remarks 1. This specification is valid only when CSI00s peripheral I/O redirect function is not used.
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register 0 (SPS0) and the CKS00 bit of serial mode
register 00 (SMR00).)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 32 of 106
RL78/G12
<R> (3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
Symbol
Conditions
HS (high-speed
LS (low-speed main)
main) Mode
Mode
MIN.
SCKp cycle time
tKCY1
tKCY1 4/fCLK
167
500
ns
250
500
ns
500
ns
tKCY1/212
tKCY1/250
ns
tKL1
tKCY1/218
tKCY1/250
ns
tKCY1/238
tKCY1/250
ns
tKCY1/250
ns
44
110
ns
44
110
ns
75
110
ns
110
ns
19
19
ns
tSIK1
tKSI1
Note 2
MAX.
MIN.
tKH1,
Note 1
MAX.
Unit
tKSO1
C = 30 pF
Note4
25
25
ns
Note 3
Notes 1.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes to
SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes from
SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes from SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins
by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1,
POM4).
Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: 1, 3 is
only for the R5F102 products)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: 1, 3 is only for the
R5F102 products.))
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 33 of 106
RL78/G12
<R> (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
Symbol
Conditions
HS (high-speed
LS (low-speed main)
main) Mode
Mode
MIN.
SCKp cycle time
Note4
tKCY2
MAX.
MIN.
Unit
MAX.
8/fMCK
ns
fMCK 20 MHz
6/fMCK
6/fMCK
ns
8/fMCK
ns
fMCK 16 MHz
6/fMCK
6/fMCK
ns
6/fMCK
6/fMCK
ns
and 500
and 500
6/fMCK
ns
and 750
SCKp high-/low-level
tKH2,
tKCY2/27
tKCY2/27
ns
width
tKL2
tKCY2/28
tKCY2/28
ns
tKCY2/218
tKCY2/218
ns
tKCY2/218
ns
1/fMCK +
1/fMCK +
ns
20
30
1/fMCK +
1/fMCK +
30
30
1/fMCK +
tSIK2
Note 1
ns
ns
30
SIp hold time
(from SCKp)
tKSI2
Note 2
tKSO2
C = 30 pF
Note4
SCKp to
SOp output
Note 3
1/fMCK +
1/fMCK +
31
31
ns
2/fMCK +
2/fMCK +
44
110
2/fMCK +
2/fMCK +
75
110
2/fMCK +
ns
ns
ns
110
Notes 1.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes to
SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes from
SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes from SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4.
5.
Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin
by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1,
POM4).
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 34 of 106
RL78/G12
SCK
SCKp
RL78
microcontroller
SIp
SO User's device
SOp
SI
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Output data
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Output data
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 35 of 106
RL78/G12
Remarks 1.
p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: 1, 3 is
only for the R5F102 products.)
2.
Symbol
Conditions
Unit
fSCL
MAX.
400
Note 1
kHz
300
Note 1
kHz
Cb = 100 pF, Rb = 3 k
1.8 V VDD < 2.7 V,
Cb = 100 pF, Rb = 5 k
Hold time when SCLr = L
tLOW
1150
ns
1550
ns
1150
ns
1550
ns
Cb = 100 pF, Rb = 3 k
1.8 V VDD < 2.7 V,
Cb = 100 pF, Rb = 5 k
Hold time when SCLr = H
tHIGH
tSU:DAT
tHD:DAT
1/fMCK + 145
Note
ns
Note
ns
1/fMCK + 230
2
355
ns
405
ns
Cb = 100 pF, Rb = 3 k
1.8 V VDD < 2.7 V,
Cb = 100 pF, Rb = 5 k
Notes 1.
<R>
2.
Caution Select the N-ch open drain output (VDD tolerance) mode for SDAr by using port output mode register
h (POMh).
(Remarks are listed on the next page.)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 36 of 106
RL78/G12
SDAr
RL78
microcontroller
User's device
SCLr
SCL
tHIGH
SCLr
SDAr
tHD:DAT
Remarks 1.
tSU:DAT
2.
3.
4.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 37 of 106
RL78/G12
Symbol
Conditions
HS (high-speed
main) Mode
MIN.
Transfer
Note4
rate
Reception
MAX.
MIN.
Unit
MAX.
fMCK/6
fMCK/6
2.7 V Vb 4.0 V
Note1
Note1
4.0
1.3
Mbps
fMCK/6
fMCK/6
bps
2.3 V Vb 2.7 V
Note1
Note1
4.0
1.3
Mbps
bps
fMCK/6
fMCK/6
Notes1, 2
Notes1, 2
4.0
1.3
Mbps
Note4
Note4
bps
Mbps
bps
Note3
Transmission
LS (low-speed
main) Mode
Note3
2.8
2.8
Note5
Note5
Note6
Note6
bps
Mbps
2.3 V Vb 2.7 V,
1.2
1.2
Note7
Note7
Notes
2, 8
Notes
2, 8
bps
0.43
0.43
Mbps
Note9
Note9
<R>
Notes 1.
<R>
2.
<R>
3.
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
4.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V VDD 5.5 V and 2.7 V Vb 4.0 V
Maximum transfer rate =
1
2.2
{Cb Rb ln (1 Vb )} 3
[bps]
1
2.2
{Cb Rb ln (1 Vb )}
Transfer rate 2
1
( Transfer rate ) Number of transferred bits
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 38 of 106
RL78/G12
<R>
5.
<R>
6.
This value as an example is calculated when the conditions described in the Conditions column are met.
Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V VDD < 4.0 V and 2.3 V Vb 2.7 V
Maximum transfer rate =
1
2.0
{Cb Rb ln (1 Vb )} 3
[bps]
1
2.0
{Cb Rb ln (1 Vb )}
Transfer rate 2
1
( Transfer rate ) Number of transferred bits
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
<R>
7.
This value as an example is calculated when the conditions described in the Conditions column are met.
Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.
<R>
8.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V
Maximum transfer rate =
1
1.5
{Cb Rb ln (1 Vb )} 3
[bps]
1
1.5
{Cb Rb ln (1 Vb )}
Transfer rate 2
1
( Transfer rate ) Number of transferred bits
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
<R>
9.
This value as an example is calculated when the conditions described in the Conditions column are met.
Refer to Note 8 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for
the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see the DC characteristics with TTL input buffer selected.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 39 of 106
RL78/G12
TxDq
RL78
microcontroller
User's device
RxDq
Tx
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
<R>
Remarks 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance,
Vb[V]: Communication line voltage
<R>
<R>
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 40 of 106
RL78/G12
<R> (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCK00... internal clock output,
corresponding CSI00 only)
(TA = 40 to +85C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
LS (low-speed
main) Mode
main) Mode
MIN.
SCK00 cycle time
tKCY1
tKCY1 2/fCLK
MAX.
MIN.
Unit
MAX.
200
1150
ns
300
1150
ns
tKCY1/2
tKCY1/2
ns
50
50
tKCY1/2
tKCY1/2
120
120
tKCY1/2
tKCY1/2
50
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
SCK00 high-level width
tKH1
tKL1
(to SCK00)
tSIK1
Note 1
ns
tKCY1/2
tKCY1/2
Cb = 20 pF, Rb = 2.7 k
10
50
58
479
ns
121
479
ns
10
10
ns
10
10
ns
ns
ns
Cb = 20 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
tKSI1
Note 1
tKSO1
Note 1
60
60
ns
130
130
ns
Cb = 20 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
tSIK1
Note 2
23
110
ns
33
110
ns
10
10
ns
10
10
ns
Cb = 20 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
tKSI1
Note 2
tKSO1
Note 2
10
10
ns
10
10
ns
Cb = 20 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 41 of 106
RL78/G12
<R>
Notes 1.
2.
Caution Select the TTL input buffer for the SI00 pin and the N-ch open drain output (VDD tolerance) mode for
the SO00 pin and SCK00 pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. Rb []:Communication line (SCK00, SO00) pull-up resistance, Cb [F]: Communication line (SCK00, SO00)
load capacitance, Vb [V]: Communication line voltage
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register 0 (SPS0) and the CKS00 bit of serial mode
register 00 (SMR00).)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 42 of 106
RL78/G12
<R> (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (1/3)
(TA = 40 to +85C, 1.8 V VDD VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
LS (low-speed main)
Mode
Mode
MIN.
SCKp cycle time
tKCY1
tKCY1 4/fCLK
MAX.
MIN.
Unit
MAX.
300
1150
ns
500
1150
ns
1150
1150
ns
tKCY1/2 75
tKCY1/275
ns
tKCY1/2 170
tKCY1/2170
ns
tKCY1/2 458
tKCY1/2458
ns
tKCY1/2 12
tKCY1/250
ns
tKCY1/2 18
tKCY1/250
ns
tKCY1/2 50
tKCY1/250
ns
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V VDD < 3.3 V,
1.6 V Vb 2.0 V
Note
Cb = 30 pF, Rb = 5.5 k
SCKp high-level width
tKH1
Note
Cb = 30 pF, Rb = 5.5 k
SCKp low-level width
tKL1
Note
Cb = 30 pF, Rb = 5.5 k
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 43 of 106
RL78/G12
<R> (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (2/3)
Symbol
Conditions
HS (high-speed
LS (low-speed
main) Mode
main) Mode
MIN.
SIp setup time
(to SCKp)
tSIK1
Note 1
MAX.
MIN.
Unit
MAX.
81
479
ns
177
479
ns
479
479
ns
19
19
ns
19
19
ns
19
19
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V
Note 2
Cb = 30 pF, Rb = 5.5 k
SIp hold time
(from SCKp)
tKSI1
Note 1
Note 2
Cb = 30 pF, Rb = 5.5 k
Delay time from
tKSO1
SCKp to
100
100
ns
195
195
ns
483
483
ns
Cb = 30 pF, Rb = 1.4 k
SOp output
Note 1
Note 2
Cb = 30 pF, Rb = 5.5 k
<R>
Notes 1.
<R>
2.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 44 of 106
RL78/G12
<R> (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (3/3)
Symbol
Conditions
HS (high-speed
LS (low-speed
main) Mode
main) Mode
MIN.
SIp setup time
(to SCKp)
tSIK1
Note 1
MAX.
MIN.
Unit
MAX.
44
110
ns
44
110
ns
110
110
ns
19
19
ns
19
19
ns
19
19
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V
Note 2
Cb = 30 pF, Rb = 5.5 k
SIp hold time
(from SCKp)
tKSI1
Note 1
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V
Note 2
Cb = 30 pF, Rb = 5.5 k
Delay time from
tKSO1
SCKp to
25
25
ns
25
25
ns
25
25
ns
Cb = 30 pF, Rb = 1.4 k
SOp output
Note 1
Note 2
Cb = 30 pF, Rb = 5.5 k
<R>
Notes 1.
2.
<R>
Cautions 1.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode
for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
2.
Remarks 1.
2.
<Master>
Rb
SCKp
RL78
microcontroller
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Vb
Rb
SCK
SIp
SO
SOp
SI
User's device
Page 45 of 106
RL78/G12
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)
t KCY1
t KL1
t KH1
SCKp
t SIK1
SIp
t KSI1
Input data
t KSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Output data
Page 46 of 106
RL78/G12
<R> (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
Symbol
Conditions
HS (high-speed main)
LS (low-speed main)
Mode
Mode
MIN.
SCKp cycle time
Note 1
tKCY2
MAX.
MIN.
Unit
MAX.
12/fMCK
ns
2.7 V Vb 4.0 V
10/fMCK
ns
8/fMCK
16/fMCK
ns
fMCK 4 MHz
6/fMCK
10/fMCK
ns
16/fMCK
ns
2.3 V Vb 2.7 V
14/fMCK
ns
12/fMCK
ns
8/fMCK
16/fMCK
ns
fMCK 4 MHz
6/fMCK
10/fMCK
ns
36/fMCK
ns
1.6 V Vb 2.0 V
32/fMCK
ns
26/fMCK
ns
16/fMCK
16/fMCK
ns
fMCK 4 MHz
10/fMCK
10/fMCK
ns
Note 2
SCKp high-/low-level
tKH2,
tKCY2/2 12
tKCY2/2 50
ns
width
tKL2
tKCY2/2 18
tKCY2/2 50
ns
tKCY2/2 50
tKCY2/2 50
ns
1/fMCK + 20
1/fMCK + 30
ns
1/fMCK + 20
1/fMCK + 30
ns
1/fMCK + 30
1/fMCK + 30
ns
1/fMCK + 31
1/fMCK + 31
ns
tSIK2
Note 3
Note 2
tKSI2
Note 4
tKSO2
SCKp to SOp
output
Note 2
Note 5
Note 2
Cb = 30 pF, Rb = 5.5 k
Notes 1.
2.
3.
2/fMCK +
2/fMCK +
120
573
2/fMCK +
2/fMCK +
214
573
2/fMCK +
2/fMCK +
573
573
ns
ns
ns
4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes from
SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes from SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Cautions 1. Select the TTL input buffer for the SIp and SCKp pins and the N-ch open drain output (VDD
tolerance) mode for the SOp pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
2. CSI01 and CSI11 cannot communicate at different potential.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 47 of 106
RL78/G12
<Slave>
Rb
SCKp
RL78
microcontroller
SCK
SIp
SO
SOp
SI
User's device
Remarks 1. Rb []: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance,
Vb [V]: Communication line voltage
2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 10))
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY2
t KH2
t KL2
SCKp
t SIK2
t KSI2
Input data
SIp
t KSO2
SOp
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Output data
Page 48 of 106
RL78/G12
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY2
t KL2
t KH2
SCKp
t SIK2
SIp
t KSI2
Input data
t KSO2
SOp
Remark
Output data
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 49 of 106
RL78/G12
Symbol
Conditions
HS (high-speed
LS (low-speed
main) Mode
main) Mode
MIN.
SCLr clock frequency
fSCL
MAX.
MIN.
Unit
MAX.
400
Note1
300
Note1
kHz
400
Note1
300
Note1
kHz
300
Note1
300
Note1
kHz
Note2
tLOW
1150
1550
ns
1150
1550
ns
1550
1550
ns
675
610
ns
600
610
ns
610
610
ns
1/fMCK
1/fMCK
ns
+ 190
+ 190
Note3
Note3
1/fMCK
1/fMCK
+ 190
+ 190
Note3
Note3
1/fMCK
1/fMCK
+ 190
+ 190
Note3
Note3
Note2
tHIGH
Note2
tSU:DAT
Note2
tHD:DAT
ns
ns
355
355
ns
355
355
ns
405
405
ns
(transmission)
Note2
<R>
<R>
Notes 1.
2.
3.
Set tSU:DAT so that it will not exceed the hold time when SCLr = "L" or SCLr = "H".
Cautions 1. Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin
and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode
register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
2. IIC01 and IIC11 cannot communicate at different potential.
(Remarks are listed on the next page.)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 50 of 106
RL78/G12
Vb
Rb
Rb
SDA
SDAr
RL78
microcontroller
User's device
SCLr
SCL
t HIGH
SCLr
SDAr
t HD : DAT
Remarks 1.
t SU : DAT
Rb []: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr)
load capacitance, Vb [V]: Communication line voltage
2.
3.
4.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 51 of 106
RL78/G12
Symbol
Conditions
Unit
MAX.
Fast Mode
MIN.
MAX.
400
fSCL
tSU:STA
4.7
0.6
tHD:STA
4.0
0.6
tLOW
4.7
1.3
tHIGH
4.0
0.6
tSU:DAT
250
100
ns
tHD:DAT
tSU:STO
4.0
0.6
Bus-free time
tBUF
4.7
1.3
Hold time
Note 1
Notes 1.
2.
Note 2
100
3.45
kHz
kHz
0.9
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution
Only in the 30-pin products, the values in the above table are applied even when bit 2 (PIOR2) in the
peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1,
VOL1) must satisfy the values in the redirect destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Normal mode:
Fast mode:
<R>
tR
SCLA0
tHD:DAT
tHD:STA
t HIGH
tF
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDAA0
t BUF
Stop
condition
Start
condition
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Restart
condition
Stop
condition
Page 52 of 106
RL78/G12
Reference Voltage
Reference voltage (+) = AVREFP
ANI0 to ANI3
ANI16 to ANI22
Temperature sensor
output voltage
<R> (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () = AVREFM/ANI1
(ADREFM = 1), target pin: ANI2, ANI3, internal reference voltage, and temperature sensor output voltage
(TA = 40 to +85C, 1.8 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage () =
AVREFM = 0 V)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
Overall error
AINL
Conversion time
tCONV
Notes 1, 2
Notes 1, 2
Full-scale error
Note 1
EZS
EFS
ILE
DLE
Note 1
VAIN
TYP.
8
10-bit resolution
Note 3
AVREFP = VDD
10-bit resolution
Target pin: ANI2, ANI3
10-bit resolution
Target pin: Internal
reference voltage, and
temperature sensor
output voltage
(HS (high-speed main)
mode)
Zero-scale error
MIN.
1.2
MAX.
Unit
10
bit
3.5
LSB
7.0
1.2
Note 4
LSB
2.125
39
3.1875
39
17
39
57
95
2.375
39
3.5625
39
17
39
0.25
%FSR
10-bit resolution
Note 3
AVREFP = VDD
0.50
0.25
10-bit resolution
Note 3
AVREFP = VDD
0.50
Note 4
2.5
10-bit resolution
Note 3
AVREFP = VDD
5.0
Note 4
1.5
10-bit resolution
Note 3
AVREFP = VDD
ANI2, ANI3
Note 4
2.0
0
Note 4
AVREFP
Note 5
VBGR
VTMPS25
Note 5
%FSR
%FSR
%FSR
LSB
LSB
LSB
LSB
V
V
V
Page 53 of 106
RL78/G12
<R>
<R>
<R> (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () = AVREFM/ANI1
(ADREFM = 1), target pin: ANI16 to ANI22
(TA = 40 to +85C, 1.8 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage () =
AVREFM = 0 V)
Parameter
Symbol
Resolution
Conditions
RES
Overall error
Note 1
AINL
tCONV
10-bit resolution
1.2
Note 3
1.2
Zero-scale error
Notes 1, 2
EZS
Notes 1, 2
EFS
Note
ILE
Differential linearity
error
DLE
Note 1
VAIN
5.0
LSB
8.5
Note 4
LSB
39
17
39
57
95
0.35
Note 3
0.60
Note 4
0.35
Note 3
0.60
Note 4
3.5
Note 3
6.0
Note 4
2.0
Note 3
ANI16 to ANI22
bit
3.1875
10-bit resolution
AVREFP = VDD
10
10-bit resolution
AVREFP = VDD
Unit
39
10-bit resolution
AVREFP = VDD
MAX.
2.125
10-bit resolution
AVREFP = VDD
Full-scale error
TYP.
8
AVREFP = VDD
Conversion time
MIN.
2.5
0
Note 4
AVREFP
%FSR
%FSR
%FSR
%FSR
LSB
LSB
LSB
LSB
V
and VDD
<R>
<R>
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 54 of 106
RL78/G12
<R> (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage () = VSS (ADREFM = 0),
target pin: ANI0 to ANI3, ANI16 to ANI22, internal reference voltage, and temperature sensor output voltage
(TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage () = VSS)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
Overall error
AINL
MIN.
TYP.
8
10-bit resolution
1.2
1.2
Conversion time
tCONV
tCONV
Unit
10
bit
7.0
LSB
10.5
Note 3
LSB
10-bit resolution
2.125
39
3.1875
39
17
39
57
95
2.375
39
3.5625
39
17
39
0.60
%FSR
0.85
%FSR
ANI16 to ANI22
Conversion time
MAX.
10-bit resolution
Zero-scale error
EZS
10-bit resolution
Note 3
Notes 1, 2
Full-scale error
EFS
10-bit resolution
0.60
%FSR
0.85
%FSR
Note 3
Note 1
ILE
4.0
10-bit resolution
6.5
Differential linearity error
Note 1
DLE
2.0
10-bit resolution
2.5
Analog input voltage
VAIN
Note 3
Note 3
VDD
VBGR
Note 4
LSB
LSB
LSB
LSB
V
V
VTMPS25
Note 4
<R>
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 55 of 106
RL78/G12
<R> (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage () =
AVREFM (ADREFM = 1), target pin: ANI0, ANI2, ANI3, and ANI16 to ANI22
(TA = 40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage () = AVREFM
Note 4
Symbol
Resolution
Conditions
MIN.
RES
Conversion time
Notes 1, 2
Zero-scale error
Note 1
Note 1
TYP.
MAX.
Unit
bit
39
8-bit resolution
0.60
%FSR
ILE
8-bit resolution
2.0
LSB
DLE
8-bit resolution
1.0
LSB
tCONV
8-bit resolution
EZS
VAIN
17
VBGR
Note 3
<R>
R01DS0193EJ0200 Rev.2.00
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Page 56 of 106
RL78/G12
Parameter
Symbol
VTMPS25
Conditions
MIN.
TYP.
MAX.
1.05
Unit
V
TA = +25C
Internal reference voltage
VBGR
Temperature coefficient
FVTMPS
1.38
1.45
1.50
3.6
mV/C
tAMP
Parameter
Symbol
Detection voltage
<R>
Note
Note
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
1.47
1.51
1.55
VPDR
1.46
1.50
1.54
TPW
300
Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required
for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or
the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation
status control register (CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
R01DS0193EJ0200 Rev.2.00
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Page 57 of 106
RL78/G12
Parameter
Detection supply voltage
Symbol
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VLVD8
VLVD9
VLVD10
VLVD11
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
tLW
Conditions
MIN.
TYP.
MAX.
Unit
3.98
4.06
4.14
3.90
3.98
4.06
3.68
3.75
3.82
3.60
3.67
3.74
3.07
3.13
3.19
3.00
3.06
3.12
2.96
3.02
3.08
2.90
2.96
3.02
2.86
2.92
2.97
2.80
2.86
2.91
2.76
2.81
2.87
2.70
2.75
2.81
2.66
2.71
2.76
2.60
2.65
2.70
2.56
2.61
2.66
2.50
2.55
2.60
2.45
2.50
2.55
2.40
2.45
2.50
2.05
2.09
2.13
2.00
2.04
2.08
1.94
1.98
2.02
1.90
1.94
1.98
1.84
1.88
1.91
1.80
1.84
1.87
300
300
Page 58 of 106
RL78/G12
Symbol
VLVDB0
mode
VLVDB1
Conditions
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
LVIS1, LVIS0 = 0, 0
VLVDB3
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
VLVDC2
LVIS1, LVIS0 = 0, 0
VLVDC3
Unit
1.80
1.84
1.87
1.94
1.98
2.02
1.90
1.94
1.98
2.05
2.09
2.13
2.00
2.04
2.08
3.07
3.13
3.19
3.00
3.06
3.12
2.40
2.45
2.50
2.56
2.61
2.66
2.50
2.55
2.60
2.66
2.71
2.76
2.60
2.65
2.70
3.68
3.75
3.82
3.60
3.67
3.74
VLVDD1
VLVDD2
VLVDD3
<R>
MAX.
VLVDC1
VLVDD0
TYP.
VLVDB2
VLVDC0
MIN.
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
LVIS1, LVIS0 = 0, 0
2.70
2.75
2.81
2.86
2.92
2.97
2.80
2.86
2.91
2.96
3.02
3.08
2.90
2.96
3.02
3.98
4.06
4.14
3.90
3.98
4.06
Caution
Symbol
Conditions
SVDD
MIN.
TYP.
MAX.
Unit
54
V/ms
Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the
operating voltage range shown in 2.4 AC Characteristics.
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Page 59 of 106
RL78/G12
2.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = 40 to +85C, VSS = 0 V)
Parameter
Data retention supply voltage
Symbol
Conditions
VDDDR
MIN.
1.46
TYP.
Note
MAX.
Unit
5.5
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR
reset is affected, but data is not retained when a POR reset is affected.
Operation mode
STOP mode
Data retention mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
Symbol
fCLK
Cerwr
Conditions
MIN.
TYP.
1
Retained for 20 years
TA = 85C
1,000
TA = 25C
TA = 85C
100,000
TA = 85C
10,000
MAX.
Unit
24
MHz
Times
Notes 1, 2, 3
1,000,000
Notes 1, 2, 3
Notes 1.
1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the
rewrite.
2.
When using flash memory programmer and Renesas Electronics self programming library
3.
These are the characteristics of the flash memory and the results obtained from reliability testing by
Renesas Electronics Corporation.
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Page 60 of 106
RL78/G12
Symbol
Transfer rate
Conditions
MIN.
TYP.
115,200
MAX.
Unit
1,000,000
bps
<R>
Symbol
Conditions
MIN.
TYP.
tSUINIT
MAX.
Unit
100
ms
reset release
Time to release the external reset after the TOOL0 tSU
10
ms
reset release
Time to hold the TOOL0 pin at the low level after
tHD
reset release
<1>
<2>
<4>
<3>
RESET
tHD + software
processing
time
<R>
TOOL0
tSU
tSUINIT
<R>
rate setting.
Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released
during this period.
<R>
tSU:
Time to release the external reset after the TOOL0 pin is set to the low level
tHD:
Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing
time of the firmware to control the flash memory)
R01DS0193EJ0200 Rev.2.00
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Page 61 of 106
RL78/G12
<R>
Application
A: Consumer applications,
G: Industrial applications
D: Industrial applications
Operating ambient temperature
TA = -40 to +85C
TA = -40 to +105C
Operating mode
accuracy
UART
UART
CSI: fCLK/2 (supporting 12 Mbps), fCLK/4
2
Voltage detector
Remark
CSI: fCLK/4
2
Simplified I C communication
Simplified I C communication
(12 levels)
(8 levels)
(12 levels)
(8 levels)
The electrical characteristics of the products G: Industrial applications (TA = -40 to +105C) are different from
those of the products A: Consumer applications, and D: Industrial applications. For details, refer to 3.1 to
3.10.
R01DS0193EJ0200 Rev.2.00
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RL78/G12
Symbols
Supply Voltage
VDD
VIREGC
Conditions
REGC
Ratings
Unit
0.5 to + 6.5
0.3 to +2.8
Input Voltage
VI1
VI2
Output Voltage
VO
VAI
IOH1
Note 3
0.3 to 6.5
0.3 to VDD + 0.3
and 0.3 to
Notes 3, 4
AVREF(+)+0.3
Note 3
Per pin
40
mA
170
mA
70
mA
100
mA
P20 to P23
0.5
mA
mA
IOH2
Per pin
Total of all pins
IOL1
Per pin
40
mA
170
mA
70
mA
100
mA
mA
mA
Note 5
Per pin
Total of all pins
P20 to P23
Operating ambient
temperature
TA
40 to +105
Storage temperature
Tstg
65 to +150
Notes 1.
2.
3.
4.
5.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
2. AVREF (+): + side reference voltage of the A/D converter.
3. VSS: Reference voltage
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Page 63 of 106
RL78/G12
frequency (fX)
Resonator
Ceramic resonator /
crystal oscillator
Conditions
MIN.
TYP.
MAX.
1.0
20.0
1.0
8.0
Unit
MHz
Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1
clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC)
by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation
stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time
with the resonator to be used.
Remark
When using the X1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G12 Users Manual
Hardware.
Parameters
Conditions
MAX.
Unit
24
MHz
TA = 20 to +85C
-1.0
+1.0
TA = 40 to 20C
-1.5
+1.5
TA = +85 to +105C
-2.0
+2.0
fIH
MIN.
TYP.
Notes 1, 2
R5F102 products
15
fIL
kHz
clock frequency
Low-speed on-chip oscillator
-15
+15
Notes 1.
High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of
HOCODIV register.
2.
This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.
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RL78/G12
3.3 DC Characteristics
3.3.1 Pin characteristics
(TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Note 1
IOH1
(1/4)
Conditions
MIN.
TYP.
MAX.
Unit
3.0
mA
Note 2
9.0
mA
6.0
mA
4.5
mA
27.0
mA
18.0
mA
10.0
mA
36.0
mA
0.1
mA
0.4
mA
30-pin products:
Total of P00, P01, P40, P120
(When duty 70%
Note 3
, P10 to P14
30-pin products:
Total of P10 to P17, P30, P31,
P50, P51, P147
(When duty 70%
Note 3
)
Note 3
Notes 1.
value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an
output pin.
2.
3.
4.
Caution P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41 for 24-pin products, and P00, P10
to P15, P17, and P50 for 30-pin products do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0200 Rev.2.00
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Page 65 of 106
RL78/G12
Symbol
Note 1
(2/4)
Conditions
MIN.
IOL1
Note 4
TYP.
MAX.
Unit
8.5
mA
Note 2
mA
Note 2
25.5
mA
9.0
mA
30-pin products:
1.8
mA
40.0
mA
27.0
mA
5.4
mA
65.5
mA
0.4
mA
1.6
mA
Note 3
Note 3
)
Note 3
Notes 1.
Value of current at which the device operation is guaranteed even if the current flows from an output pin to
the VSS pin.
2.
3.
The output current value under conditions where the duty factor 70%.
If duty factor > 70%: The output current value can be calculated with the following expression (where n
represents the duty factor as a percentage).
Total output current of pins = (IOL 0.7)/(n 0.01)
<Example> Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 0.7)/(80 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
4.
Remark
R01DS0193EJ0200 Rev.2.00
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RL78/G12
Symbol
VIH1
(3/4)
Conditions
MIN.
MAX.
Unit
0.8VDD
VDD
2.2
VDD
2.0
VDD
1.5
VDD
0.7VDD
VDD
0.7VDD
6.0
0.8VDD
VDD
0.2VDD
0.8
0.5
0.32
0.3VDD
0.3VDD
0.2VDD
TYP.
Note 2
, P10 to P14,
P40 to P42
30-pin products: P00, P01, P10 to P17, P30, P31,
P40, P50, P51, P120, P147
VIH2
VIH4
P60, P61
Note 1
VIH5
VIL1
Note 2
, P10 to P14,
P40 to P42
30-pin products: P00, P01, P10 to P17, P30, P31,
P40, P50, P51, P120, P147
VIL2
VIL3
P20 to P23
VIL4
P60, P61
Note 1
VIL5
VOH1
Note 2
, P10 to P14,
30-pin products:
IOH1 = 2.0 mA
P147
Notes 1.
2.
P20 to P23
VDD0.7
VDD0.6
VDD0.5
VDD0.5
IOH1 = 3.0 mA
P40 to P42
IOH1 = 1.5 mA
IOH2 = 100 A
Caution The maximum value of VIH of pins P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41
for 24-pin products, and P00, P10 to P15, P17, and P50 for 30-pin products is VDD even in N-ch opendrain mode.
High level is not output in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0200 Rev.2.00
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Page 67 of 106
RL78/G12
Symbol
VOL1
(4/4)
Conditions
20-, 24-pin products:
P00 to P03
Note
, P10 to P14,
MAX.
Unit
0.7
0.6
0.4
0.4
IOL1 = 8.5 mA
2.7 V VDD 5.5 V,
IOL1 = 3.0 mA
TYP.
P40 to P42
P10 to P17, P30, P31, P40,
MIN.
VOL2
P20 to P23
IOL2 = 400 A
0.4
VOL3
P60, P61
2.0
0.4
0.4
0.4
10
10
100
IOL1 = 15.0 mA
4.0 V VDD 5.5 V,
IOL1 = 5.0 mA
2.7 V VDD 5.5 V,
IOL1 = 3.0 mA
2.4 V VDD 5.5 V,
IOL1 = 2.0 mA
Input leakage current,
ILIH1
VI = VDD
P122
high
ILIH2
P121, P122
(X1, X2/EXCLK)
clock input
When resonator
connected
ILIL1
VI = VSS
P122
low
ILIL2
P121, P122
(X1, X2/EXCLK)
clock input
When resonator
connected
On-chip pull-up
RU
resistance
10
20
Note
, P10 to P14,
Note
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0200 Rev.2.00
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RL78/G12
Symbol
IDD1
Note 1
(1/2)
Conditions
Operating HS (High-speed
mode
main) mode
MIN.
Note 3
Basic
fIH = 24 MHz
Note 4
VDD = 5.0 V
1.5
1.5
Normal
3.3
5.3
3.3
5.3
VDD = 5.0 V
2.5
3.9
VDD = 3.0 V
2.5
3.9
2.8
4.7
Resonator connection
3.0
4.8
2.8
4.7
Resonator connection
3.0
4.8
1.8
2.8
Resonator connection
1.8
2.8
1.8
2.8
Resonator connection
1.8
2.8
Note 2
VDD = 5.0 V
Note 2
VDD = 3.0 V
Note 2
fMX = 10 MHz
VDD = 5.0 V
Note 2
fMX = 10 MHz
VDD = 3.0 V
Notes 1.
Unit
mA
VDD = 5.0 V
Note 3
fMX = 20 MHz
MAX.
fMX = 20 MHz
TYP.
mA
mA
mA
mA
mA
mA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
2.
3.
4.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
R01DS0193EJ0200 Rev.2.00
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RL78/G12
Symbol
IDD2
Note 2
Note 1
(2/2)
Conditions
HALT
mode
HS (High-speed
main) mode
fIH = 24 MHz
Note 4
fIH = 16 MHz
Note 4
MIN.
Note 6
fMX = 20 MHz
Note 3
VDD = 5.0 V
fMX = 20 MHz
IDD3
Notes 1.
VDD = 5.0 V
440
2230
VDD = 3.0 V
440
2230
VDD = 5.0 V
400
1650
VDD = 3.0 V
400
1650
280
1900
450
2000
280
1900
Resonator connection
450
2000
Note 3
190
1010
Resonator connection
260
1090
190
1010
Resonator connection
260
1090
Note 3
VDD = 3.0 V
Note 5
Unit
Resonator connection
VDD = 5.0 V
fMX = 10 MHz
MAX.
Note 3
VDD = 3.0 V
fMX = 10 MHz
TYP.
STOP
TA = 40C
0.19
0.50
mode
TA = +25C
0.24
0.50
TA = +50C
0.32
0.80
TA = +70C
0.48
1.20
TA = +85C
0.74
2.20
TA = +105C
1.50
10.20
A
A
A
A
A
A
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
2.
3.
4.
5.
Not including the current flowing into the 12-bit interval timer and watchdog timer.
6.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
R01DS0193EJ0200 Rev.2.00
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RL78/G12
Symbol
IDD1
Note 1
(1/2)
Conditions
Operating
mode
main) mode
MIN.
Basic
Note 4
VDD = 5.0 V
1.5
1.5
Normal
MAX.
VDD = 5.0 V
3.7
5.8
3.7
5.8
VDD = 5.0 V
2.7
4.2
fIH = 16 MHz
VDD = 3.0 V
2.7
4.2
Note 2
3.0
4.9
Resonator connection
3.2
5.0
Note 2
3.0
4.9
Resonator connection
3.2
5.0
1.9
2.9
Resonator connection
1.9
2.9
1.9
2.9
Resonator connection
1.9
2.9
fMX = 20 MHz
VDD = 5.0 V
fMX = 20 MHz
VDD = 3.0 V
Note 2
fMX = 10 MHz
VDD = 5.0 V
Note 2
fMX = 10 MHz
VDD = 3.0 V
Unit
mA
Notes 1.
TYP.
mA
mA
mA
mA
mA
mA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
2.
3.
4.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
R01DS0193EJ0200 Rev.2.00
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RL78/G12
Symbol
IDD2
(2/2)
Conditions
Note 2
Note 1
HALT
HS (High-speed
mode
Note 6
main) mode
fIH = 24 MHz
Note 4
fIH = 16 MHz
Note 4
fMX = 20 MHz
MIN.
Note 3
VDD = 5.0 V
fMX = 20 MHz
IDD3
Notes 1.
VDD = 5.0 V
440
2300
VDD = 3.0 V
440
2300
VDD = 5.0 V
400
1700
VDD = 3.0 V
400
1700
280
1900
450
2000
280
1900
Resonator connection
450
2000
Note 3
190
1020
Resonator connection
260
1100
190
1020
Resonator connection
260
1100
Note 3
VDD = 3.0 V
Note 5
Unit
Resonator connection
VDD = 5.0 V
fMX = 10 MHz
MAX.
Note 3
VDD = 3.0 V
fMX = 10 MHz
TYP.
STOP
TA = 40C
0.18
0.50
mode
TA = +25C
0.23
0.50
TA = +50C
0.30
1.10
TA = +70C
0.46
1.90
TA = +85C
0.75
3.30
TA = +105C
2.94
15.30
A
A
A
A
A
A
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
2.
3.
4.
5.
Not including the current flowing into the 12-bit interval timer and watchdog timer.
6.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
R01DS0193EJ0200 Rev.2.00
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RL78/G12
Symbol
IFIL
Conditions
MIN.
Note 1
TYP.
MAX.
Unit
0.20
0.02
0.22
oscillator operating
current
12-bit interval timer
ITMKA
operating current
Notes 1, 2, 3
Watchdog timer
IWDT
operating current
Notes 1, 2, 4
A/D converter
operating current
A/D converter
reference voltage
operating current
Temperature sensor
operating current
LVD operating current
ADC
Notes 1, 5
fIL = 15 kHz
When conversion
at maximum speed
1.30
1.70
mA
0.50
0.70
mA
75.0
75.0
ILVD
0.08
IADREF
Note 1
TMPS
Note 1
Notes 1, 6
Self-programming
IFSP
operating current
Notes 1, 8
BGO operating
IBGO
current
Notes 1, 7
SNOOZE operating
ISNOZ
current
Note 1
ADC operation
Note 9
2.00
12.20
mA
2.00
12.20
mA
0.50
1.10
mA
1.20
2.04
mA
0.70
1.54
mA
R01DS0193EJ0200 Rev.2.00
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RL78/G12
3.4 AC Characteristics
(TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V)
Items
Instruction cycle (minimum
Symbol
TCY
Conditions
fEX
frequency
External main system clock
tEXH, tEXL
0.04167
speed main)
operation
mode
0.0625
During self
HS (High-
0.04167
programming
speed main)
0.0625
1.0
20.0
MHz
1.0
16.0
MHz
24
ns
30
ns
1/fMCK +
ns
10
fTO
fPCL
output frequency
Unit
HS (High-
tTIH, tTIL
frequency
PCLBUZ0, or PCLBUZ1
MAX.
clock (fMAIN)
TYP.
Main system
mode
External main system clock
MIN.
12
MHz
MHz
MHz
16
MHz
MHz
MHz
tKR
250
ns
tRSL
10
tINTH, tINTL
Remark
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RL78/G12
10
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.1
0.0625
0.04167
0.01
0
1.0
2.0
3.0
2.4 2.7
4.0
5.0
5.5
6.0
Test points
VIL/VOL
VIH/VOH
VIL/VOL
tEXH
EXCLK
R01DS0193EJ0200 Rev.2.00
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RL78/G12
TI/TO Timing
tTIH
tTIL
TI00 to TI07
1/fTO
TO00 to TO07
tINTL
INTP0 to INTP5
KR0 to KR9
RESET
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RL78/G12
VIH/VOH
Test points
VIL/VOL
VIL/VOL
Symbol
Conditions
Transfer rate
Note 1
MAX.
fMCK/12
bps
2.0
Mbps
Notes 1.
2.
Unit
Note2
Caution
Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
Rx
TxDq
RL78
microcontroller
User's device
RxDq
Tx
TxDq
RxDq
Remarks 1.
2.
R01DS0193EJ0200 Rev.2.00
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Page 77 of 106
RL78/G12
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
Symbol
Conditions
tKCY1
Note 1
Note 2
tKCY1 4/fCLK
Unit
MAX.
334
ns
500
ns
tKH1,
tKCY1/224
ns
tKL1
tKCY1/236
ns
tKCY1/276
ns
66
ns
66
ns
113
ns
38
ns
tSIK1
tKSI1
tKSO1
C = 30 pF
Note4
50
ns
Note 3
Notes 1.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes to
SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes from
SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes from SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins
by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1,
POM4).
Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3))
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RL78/G12
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
Symbol
Conditions
Note4
tKCY2
Unit
MAX.
16/fMCK
ns
fMCK 20 MHz
12/fMCK
ns
16/fMCK
ns
fMCK 16 MHz
12/fMCK
ns
12/fMCK
ns
and 1000
SCKp high-/low-level width
tKH2,
tKCY2/214
ns
tKL2
tKCY2/216
ns
tSIK2
Note 1
tKCY2/236
ns
1/fMCK + 40
ns
1/fMCK + 60
ns
1/fMCK + 62
ns
tKSI2
Note 2
tKSO2
C = 30 pF
Note4
Note 3
Notes 1.
2/fMCK + 66
ns
2/fMCK + 113
ns
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes to
SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes from
SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes from SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4.
5.
Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin
by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1,
POM4).
CSI mode connection diagram (during communication at same potential)
SCKp
RL78
microcontroller
SIp
SOp
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
SCK
SO User's device
SI
Page 79 of 106
RL78/G12
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Output data
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial
mode register mn (SMRmn). m: Unit number (m = 0,1), n: Channel number (n = 0, 1, 3))
R01DS0193EJ0200 Rev.2.00
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RL78/G12
Symbol
Conditions
fSCL
Cb = 100 pF, Rb = 3 k
tLOW
Cb = 100 pF, Rb = 3 k
4600
tHIGH
Cb = 100 pF, Rb = 3 k
4600
tSU:DAT
Cb = 100 pF, Rb = 3 k
tHD:DAT
Cb = 100 pF, Rb = 3 k
Notes 1.
2.
MAX.
100
1/fMCK + 580
Unit
Note 1
kHz
ns
ns
Note 2
ns
1420
ns
Caution Select the N-ch open drain output (VDD tolerance) mode for SDAr by using port output mode register
h (POMh).
SDAr
RL78
microcontroller
User's device
SCLr
SCL
tHIGH
SCLr
SDAr
tHD:DAT
Remarks 1.
tSU:DAT
2.
3.
R01DS0193EJ0200 Rev.2.00
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Page 81 of 106
RL78/G12
Symbol
HS (high-speed main)
Conditions
Unit
Mode
MIN.
Reception
Transfer
rate
MAX.
fMCK/12
2.0
Mbps
fMCK/12
bps
Note 1
2.3 V Vb 2.7 V
2.0
Mbps
fMCK/12
bps
1.6 V Vb 2.0 V
Note 1
Note 2
bps
Note 1
2.7 V Vb 4.0 V
Note4
2.0
Mbps
Note 3
bps
2.0
Mbps
Note 2
Note 4
Note 5
bps
1.2
Mbps
2.3 V Vb 2.7 V,
Theoretical value of the maximum
transfer rate
Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V
Note 6
Notes 1.
2.
Notes
2, 7
bps
0.43
Mbps
Note 8
3.
The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V VDD 5.5 V and 2.7 V Vb 4.0 V
Maximum transfer rate =
1
2.2
{Cb Rb ln (1 Vb )} 3
[bps]
1
2.2
{Cb Rb ln (1 Vb )}
Transfer rate 2
1
( Transfer rate ) Number of transferred bits
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
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RL78/G12
4.
This value as an example is calculated when the conditions described in the Conditions column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
5.
The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V VDD < 4.0 V and 2.3 V Vb 2.7 V
Maximum transfer rate =
1
2.0
{Cb Rb ln (1 Vb )} 3
[bps]
1
2.0
{Cb Rb ln (1 Vb )}
Transfer rate 2
1
( Transfer rate ) Number of transferred bits
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
6.
This value as an example is calculated when the conditions described in the Conditions column are met.
7.
The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer.
maximum transfer rate.
Expression for calculating the transfer rate when 2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V
Maximum transfer rate =
1
1.5
{Cb Rb ln (1 Vb )} 3
[bps]
1.5
1
{Cb Rb ln (1 Vb )}
Transfer rate 2
1
( Transfer rate ) Number of transferred bits
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
8.
This value as an example is calculated when the conditions described in the Conditions column are met.
Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for
the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see the DC characteristics with TTL input buffer selected.
R01DS0193EJ0200 Rev.2.00
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Page 83 of 106
RL78/G12
TxDq
RL78
microcontroller
User's device
RxDq
Tx
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remarks 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance,
Vb[V]: Communication line voltage
2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))
4. UART0 of the 20- and 24-pin products supports communication at different potential only when the
peripheral I/O redirection function is not used.
R01DS0193EJ0200 Rev.2.00
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RL78/G12
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (1/3)
(TA = 40 to +105C, 2.4 V VDD VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
tKCY1
tKCY1 4/fCLK
Unit
MAX.
600
ns
1000
ns
2300
ns
tKCY1/2 150
ns
tKCY1/2 340
ns
tKCY1/2 916
ns
tKCY1/2 24
ns
tKCY1/2 36
ns
tKCY1/2 100
ns
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2.4 V VDD < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
SCKp high-level width
tKH1
tKL1
Cautions 1.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode
for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
2.
Remarks 1.
2.
R01DS0193EJ0200 Rev.2.00
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RL78/G12
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (2/3)
Symbol
Conditions
tSIK1
Note
Unit
MAX.
162
ns
354
ns
958
ns
38
ns
38
ns
38
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
tKSI1
Note
tKSO1
Note
200
ns
390
ns
966
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
Note
R01DS0193EJ0200 Rev.2.00
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Page 86 of 106
RL78/G12
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (3/3)
Symbol
Conditions
tSIK1
Note
Unit
MAX.
88
ns
88
ns
220
ns
38
ns
38
ns
38
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
tKSI1
Note
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
tKSO1
Note
50
ns
50
ns
50
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
Note
Cautions 1.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode
for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
2.
Remarks 1.
2.
<Master>
Rb
SCKp
RL78
microcontroller
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Vb
Rb
SCK
SIp
SO
SOp
SI
User's device
Page 87 of 106
RL78/G12
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)
t KCY1
t KL1
t KH1
SCKp
t SIK1
SIp
t KSI1
Input data
t KSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
Output data
SOp
Remark
R01DS0193EJ0200 Rev.2.00
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Page 88 of 106
RL78/G12
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
Symbol
HS (high-speed main)
Conditions
Unit
Mode
MIN.
SCKp cycle time
Note 1
tKCY2
MAX.
24/fMCK
ns
2.7 V Vb 4.0 V
20/fMCK
ns
16/fMCK
ns
fMCK 4 MHz
12/fMCK
ns
32/fMCK
ns
2.3 V Vb 2.7 V
28/fMCK
ns
24/fMCK
ns
16/fMCK
ns
fMCK 4 MHz
12/fMCK
ns
72/fMCK
ns
1.6 V Vb 2.0 V
64/fMCK
ns
52/fMCK
ns
32/fMCK
ns
fMCK 4 MHz
20/fMCK
ns
SCKp high-/low-level
tKH2,
tKCY2/2 24
ns
width
tKL2
tKCY2/2 36
ns
tKCY2/2 100
ns
1/fMCK + 40
ns
1/fMCK + 40
ns
1/fMCK + 60
ns
1/fMCK + 62
ns
tSIK2
Note 2
tKSI2
Note 3
tKSO2
Note 4
2/fMCK +
2/fMCK +
2/fMCK +
Cb = 30 pF, Rb = 5.5 k
Notes 1.
2.
ns
428
Cb = 30 pF, Rb = 2.7 k
2.4 V VDD < 3.3 V, 1.6 V Vb 2.0 V,
ns
240
Cb = 30 pF, Rb = 1.4 k
ns
1146
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes from
SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes from SCKp when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Cautions
1. Select the TTL input buffer for the SIp and SCKp pins and the N-ch open drain output (VDD
tolerance) mode for the SOp pin by using port input mode register 1 (PIM1) and port output
mode register 1 (POM1).
For VIH and VIL, see the DC characteristics with TTL input buffer
selected.
2. CSI01 and CSI11 cannot communicate at different potential.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 89 of 106
RL78/G12
<Slave>
Rb
SCKp
RL78
microcontroller
SCK
SIp
SO
SOp
SI
User's device
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY2
t KH2
t KL2
SCKp
t SIK2
t KSI2
Input data
SIp
t KSO2
SOp
Output data
Remarks 1. Rb []: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance,
Vb [V]: Communication line voltage
2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn))
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 90 of 106
RL78/G12
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY2
t KL2
t KH2
SCKp
t SIK2
SIp
t KSI2
Input data
t KSO2
SOp
Remark
Output data
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 91 of 106
RL78/G12
Symbol
Conditions
HS (high-speed main)
Unit
Mode
MIN.
SCLr clock frequency
fSCL
MAX.
100
Note1
kHz
100
Note1
kHz
100
Note1
kHz
tLOW
4600
ns
4600
ns
4650
ns
2700
ns
2400
ns
1830
ns
1/fMCK
ns
tHIGH
tSU:DAT
tHD:DAT
+ 760
Note3
1/fMCK
+ 760
ns
Note3
1/fMCK
+ 570
ns
Note3
1420
ns
1420
ns
1215
ns
Notes 1.
2.
Cautions 1. Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin
and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode
register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
2. IIC01 and IIC11 cannot communicate at different potential.
(Remarks are listed on the next page.)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 92 of 106
RL78/G12
Vb
Rb
Rb
SDA
SDAr
RL78
microcontroller
User's device
SCLr
SCL
t HIGH
SCLr
SDAr
t HD : DAT
Remarks 1.
t SU : DAT
Rb []: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr)
load capacitance, Vb [V]: Communication line voltage
2.
3.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 93 of 106
RL78/G12
Symbol
Conditions
fSCL
MAX.
Unit
Fast Mode
MIN.
MAX.
400
100
kHz
kHz
tSU:STA
4.7
0.6
tHD:STA
4.0
0.6
tLOW
4.7
1.3
tHIGH
4.0
0.6
tSU:DAT
250
100
ns
tHD:DAT
tSU:STO
4.0
0.6
Bus-free time
tBUF
4.7
1.3
Hold time
Note 1
Notes 1.
2.
Note 2
3.45
0.9
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution
Only in the 30-pin products, the values in the above table are applied even when bit 2 (PIOR2) in the
peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1,
VOL1) must satisfy the values in the redirect destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Normal mode:
Fast mode:
tR
SCLA0
tHD:DAT
tHD:STA
t HIGH
tF
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDAA0
t BUF
Stop
condition
Start
condition
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Restart
condition
Stop
condition
Page 94 of 106
RL78/G12
Reference Voltage
Reference voltage (+) = AVREFP
ANI0 to ANI3
ANI16 to ANI22
Temperature sensor
output voltage
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () = AVREFM/ANI1
(ADREFM = 1), target pin: ANI2, ANI3, internal reference voltage, and temperature sensor output voltage
(TA = 40 to +105C, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage () =
AVREFM = 0 V)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
AINL
10-bit resolution
Note 3
AVREFP = VDD
Conversion time
tCONV
10-bit resolution
Target pin: ANI2, ANI3
10-bit resolution
Target pin: Internal
reference voltage, and
temperature sensor
output voltage
(HS (high-speed main)
mode)
Notes 1, 2
Notes 1, 2
Full-scale error
Note 1
1.2
MAX.
Unit
10
bit
3.5
LSB
2.125
39
3.1875
39
17
39
2.375
39
3.5625
39
17
39
EZS
10-bit resolution
Note 3
AVREFP = VDD
0.25
%FSR
EFS
10-bit resolution
Note 3
AVREFP = VDD
0.25
%FSR
ILE
10-bit resolution
Note 3
AVREFP = VDD
2.5
LSB
DLE
10-bit resolution
Note 3
AVREFP = VDD
1.5
LSB
VAIN
ANI2, ANI3
AVREFP
Note 1
TYP.
Overall error
Zero-scale error
MIN.
0
VBGR
Note 4
VTMPS25
Note 4
V
V
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 95 of 106
RL78/G12
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () = AVREFM/ANI1
(ADREFM = 1), target pin: ANI16 to ANI22
(TA = 40 to +105C, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage () =
AVREFM = 0 V)
Parameter
Symbol
Resolution
Conditions
RES
Overall error
Note 1
AINL
tCONV
10-bit resolution
1.2
Zero-scale error
EZS
Notes 1, 2
EFS
Note 1
ILE
error
DLE
Note 1
VAIN
5.0
LSB
2.125
39
39
17
39
0.35
%FSR
0.35
%FSR
3.5
LSB
2.0
LSB
AVREFP
10-bit resolution
Note 3
10-bit resolution
Note 3
10-bit resolution
Note 3
10-bit resolution
AVREFP = VDD
bit
3.1875
AVREFP = VDD
Differential linearity
10
AVREFP = VDD
Integral linearity error
Unit
10-bit resolution
AVREFP = VDD
Full-scale error
MAX.
Note 3
TYP.
8
AVREFP = VDD
Conversion time
MIN.
Note 3
ANI16 to ANI22
and VDD
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 96 of 106
RL78/G12
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage () = VSS (ADREFM = 0),
target pin: ANI0 to ANI3, ANI16 to ANI22, internal reference voltage, and temperature sensor output voltage
(TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage () = VSS)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
MIN.
TYP.
Unit
10
bit
7.0
LSB
39
Overall error
AINL
10-bit resolution
Conversion time
tCONV
10-bit resolution
2.125
3.1875
39
17
39
2.375
39
3.5625
39
17
39
ANI16 to ANI22
Conversion time
tCONV
1.2
MAX.
Zero-scale error
Notes 1, 2
Full-scale error
Note 1
Note 1
EZS
10-bit resolution
0.60
%FSR
EFS
10-bit resolution
0.60
%FSR
ILE
10-bit resolution
4.0
LSB
DLE
10-bit resolution
2.0
LSB
VAIN
VDD
VBGR
Note 3
VTMPS25
Note 3
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 97 of 106
RL78/G12
(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage () =
AVREFM (ADREFM = 1), target pin: ANI0, ANI2, ANI3, and ANI16 to ANI22
(TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage () =
AVREFM Note 4= 0 V, HS (high-speed main) mode)
Parameter
Symbol
Resolution
Conditions
MIN.
RES
Conversion time
Notes 1, 2
Zero-scale error
Note 1
Note 1
TYP.
MAX.
Unit
bit
39
8-bit resolution
0.60
%FSR
ILE
8-bit resolution
2.0
LSB
DLE
8-bit resolution
1.0
LSB
tCONV
8-bit resolution
EZS
VAIN
17
VBGR
Note 3
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 98 of 106
RL78/G12
Symbol
VTMPS25
Conditions
MIN.
TYP.
MAX.
1.05
Unit
V
TA = +25C
Internal reference voltage
VBGR
Temperature coefficient
FVTMPS
1.38
1.45
1.50
3.6
V
mV/C
tAMP
Symbol
Detection voltage
Note
Note
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
1.45
1.51
1.57
VPDR
1.44
1.50
1.56
TPW
300
Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required
for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or
the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation
status control register (CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 99 of 106
RL78/G12
Symbol
MAX.
Unit
3.90
4.06
4.22
3.83
3.98
4.13
VLVD1
3.60
3.75
3.90
3.53
3.67
3.81
3.01
3.13
3.25
2.94
3.06
3.18
2.90
3.02
3.14
2.85
2.96
3.07
VLVD4
2.81
2.92
3.03
2.75
2.86
2.97
VLVD5
2.70
2.81
2.92
2.64
2.75
2.86
2.61
2.71
2.81
2.55
2.65
2.75
2.51
2.61
2.71
2.45
2.55
2.65
VLVD6
VLVD7
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
TYP.
VLVD3
MIN.
VLVD0
VLVD2
Conditions
tLW
300
300
RL78/G12
Symbol
VLVDD0
mode
VLVDD1
Conditions
MIN.
TYP.
MAX.
Unit
2.64
2.75
2.86
2.81
2.92
3.03
2.75
2.86
2.97
2.90
3.02
3.14
2.85
2.96
3.07
3.90
4.06
4.22
3.83
3.98
4.13
VLVDD2
VLVDD3
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
LVIS1, LVIS0 = 0, 0
Caution
Symbol
Conditions
SVDD
MIN.
TYP.
MAX.
Unit
54
V/ms
Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the
operating voltage range shown in 3.4 AC Characteristics.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
RL78/G12
3.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = 40 to +105C, VSS = 0 V)
Parameter
Data retention supply voltage
Symbol
Conditions
VDDDR
MIN.
1.44
TYP.
MAX.
Unit
5.5
Note
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR
reset is affected, but data is not retained when a POR reset is affected.
Operation mode
STOP mode
Data retention mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
Symbol
fCLK
Cerwr
Conditions
MIN.
TYP.
1
Retained for 20 years
TA = 85C
1,000
TA = 25C
Notes 1, 2, 3
TA = 85C
100,000
TA = 85C
10,000
MAX.
Unit
24
MHz
Times
Notes 1, 2, 3
Notes 1.
1,000,000
1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the
rewrite.
2.
When using flash memory programmer and Renesas Electronics self programming library
3.
These are the characteristics of the flash memory and the results obtained from reliability testing by
Renesas Electronics Corporation.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
RL78/G12
Symbol
Transfer rate
Conditions
MIN.
TYP.
115,200
MAX.
Unit
1,000,000
bps
Symbol
tSUINIT
Conditions
MIN.
TYP.
MAX.
Unit
100
ms
tSU
Time to hold the TOOL0 pin at the low level after the tHD
external reset is released
10
ms
<1>
<2>
<4>
<3>
RESET
tHD + software
processing
time
TOOL0
tSU
tSUINIT
Time to release the external reset after the TOOL0 pin is set to the low level
tHD:
Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing
time of the firmware to control the flash memory)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
RL78/G12
4. PACKAGE DRAWINGS
4. PACKAGE DRAWINGS
4.1 20-pin products
<R>
<R>
RENESAS Code
Previous Code
P-LSSOP20-4.4x6.5-0.65
PLSP0020JB-A
P20MA-65-NAA-1
0.1
20
c
10
bp
A
A2
A1
HE
(UNIT:mm)
NOTE
1.Dimensions
2.Dimension
1 and
ITEM
DIMENSIONS
D
E
6.50 0.10
4.40 0.10
HE
6.40 0.20
1.45 MAX.
A1
0.10 0.10
A2
1.15
e
bp
c
L
y
0.65 0.12
0.22 0.10
0.05
0.15 0.05
0.02
0.50 0.20
0.10
0 to 10
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
RL78/G12
4. PACKAGE DRAWINGS
<R>
<R>
RENESAS Code
Previous Code
P-HWQFN24-4x4-0.50
PWQN0024KE-A
P24K8-50-CAB-1
0.04
DETAIL OF A PART
E
S
A
S
(UNIT:mm)
ITEM
D2
4.00 0.05
4.00 0.05
0.75 0.05
0.25 0.05
0.07
e
7
24
Lp
DIMENSIONS
0.50
0.40 0.10
0.05
0.05
E2
ITEM
19
12
18
EXPOSED
DIE PAD
VARIATIONS
13
D2
E2
Lp
b
S AB
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
RL78/G12
4. PACKAGE DRAWINGS
<R>
<R>
RENESAS Code
Previous Code
P-LSSOP30-0300-0.65
PLSP0030JB-B
S30MC-65-5A4-3
0.18
30
16
detail of lead end
F
G
T
P
1
15
H
I
C
D
N
M
ITEM
A
MILLIMETERS
9.85 0.15
0.45 MAX.
0.65 (T.P.)
NOTE
0.24 0.08
0.07
0.1 0.05
1.3 0.1
1.2
8.1 0.2
6.1 0.2
1.0 0.2
0.17 0.03
0.5
0.13
0.10
0.25
0.6 0.15
5
3
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Revision History
Rev.
Date
Page
1.00
2.00
Modification of Table 1-1. List of Ordering Part Numbers, Note, and Caution
7 to 9
Summary
14
17
18
18
19
20
23
24
25
26
27
28
29
Addition of Minimum Instruction Execution Time during Main System Clock Operation
30
Modification of figures of AC Timing Test Point and External Main System Clock Timing
31
31
32
33
34
36
(simplified I C mode)
38, 39
40
42
43
44
45
47
50
53
53
54
54
C-1
Description
Rev.
Date
Page
2.00
55
56
57
57
58
59
59
Modification of number and title to 2.6.5 Power supply voltage rising slope characteristics
61
Modification of table, figure, and Remark in 2.10 Timing of Entry to Flash Memory
Summary
Programming Modes
62 to 103
104 to 106
All trademarks and registered trademarks are the property of their respective owners.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Caution: This product uses SuperFlash technology licensed from Silicon Storage Technology, Inc.
C-2
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
5.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
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1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
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Tel: +44-1628-651-700, Fax: +44-1628-651-804
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Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
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