International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.

1, February 2012

High Speed, Low Power Current Comparators

with Hysteresis
Neeraj K. Chasta
Dhirubhai Ambani Institute of Iinformation & Communication Technology, Gandhinagar,
Gujarat
neeraj.chasta@gmail.com

ABSTRACT
This paper, presents a novel idea for analog current comparison which compares input signal current and
reference currents with high speed, low power and well controlled hysteresis. Proposed circuit is based on
current mirror and voltage latching techniques which produces rail to rail output voltage as a result of
current comparison. The same design can be extended to a simple current comparator without hysteresis
(or very less hysteresis), where comparator gives high accuracy (less than 50nA) and speed at the cost of
moderate power consumption. The comparators are designed optimally and studied at 180nm CMOS
process technology for a supply voltage of 3V.

KEYWORDS
Current Mode, Current Comparator, Hysteresis.

1. INTRODUCTION
Nodal voltages and branch currents represents the information carried by any electric network.
The former referred to voltage domain circuits whereas the latter are known as current domain
circuits. In recent years; as supply voltage and device threshold voltage reduction greatly
affected the performance of voltage domain circuits, current mode circuits are becoming
designers interest. Current domain circuits show many unique and attractive properties over their
voltage mode complements including higher speed, higher bandwidth, reduced distortion, low
supply voltage requirements and lesser sensitivity to switching noise.
Several current mode comparison approaches are proposed [5]-[14]. The first CMOS continuous
time current comparator was proposed in [5]. It consists of two cascode current mirrors but cant
operate at high speeds and frequencies due to high output impedance. To overcome this problem
a new circuit has been proposed [7] which uses inverter stage in feedback with source-follower
stage. But the circuit shows dead band region for low values of currents, where input impedance
is quite high and thus limits speed of operation.
The input and output impedances are further controlled by voltage-current feedback concept [12],
[14]; where a resistive feedback is applied to a voltage amplifier, thus reducing impedances and
improving speed performance. Current mirror concept again used in [15]; where it uses improved
Wilson current mirror for current comparison, but circuit suffers from higher power consumption
and delay introduced by gain circuitry.
DOI : 10.5121/vlsic.2012.3107

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012

Fig. 1: Existing Current Comparators (A) H. Traffs[7] (B) R. Dels[10] (C) L. Chens[14] (D)
V. Kasemsuwans[15]

2. COMPARATORS WITH HYSTERESIS

Z. Wang proposes current comparator with hysteresis [6] shown in fig 2. It uses three current
sources namely I1, I2 and Ihy. I1 and I2 are input currents to be compared whereas amount of
hysteresis generated decided by current Ihy.

Fig. 2: Z. Wangs Comparator (with hysteresis) [6]

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012

This circuit suffers from some major operational problems such as; functionality depends on the
digital levels generated at node A and node B, and does not provide any assistance at the
times of transitions as both of transistors M1 and M2 will be in on state. Speed performance is
low; also design needs modification for zero and negative values of currents.

3. CIRCUIT DESCRIPTION
Here a new comparison scheme is proposed which consists of three stages: the input preamplifier,
a positive feedback latch stage and an output inverter. The preamplifier stage allow the input
currents to flow through it and develop corresponding voltage at input nodes which results in
terms of current output by current mirroring concept. It also isolates the input of comparator from
switching noise (kickback noise) coming from positive feedback stage.
The latch stage determines which of the input signal is larger by positive feedback action. It is
also called as decision making stage. The inverter stage amplifies the information provided by
decision stage and outputs a CMOS compatible voltage signal (0 or VDD).

Fig. 3: Proposed Current Comparator

Working: Consider the case when Iref is constant and Iin change from low to high. A constant
Iref will keep node B at constant voltage and allow M6 to supply a constant drain current (I2) to
latch circuit. On the other hand change in Iin will make node A voltage varying and so the gate
voltage of M5.
As Iin increases, VA increases and thus reduces the drain current (I1). This decrease in I1 will
reduce current through M7 and so the voltage at node C (VC). This change will affect the
current through M9 and as I2 is constant, current through M10 will increase. As drain current of
M10 is increasing, (Vgs) of M10 will increase and so voltage at node D (VD), positive feedback
action gives produce more reduction in drain current of M7 and hence in VC. Variations at node
C are applied to inverter circuitry which results in CMOS compatible rail to rail output voltage.
The circuit uses positive feedback from the cross-gate connection of M8 and M9 to increase the
gain of latch circuitry (As circuit is symmetric gm7 = gm10 & gm8 = gm9). But if gms of all the latch
transistors are not equal, will lead circuit to show hysteresis property. This we can easily analyze
by small signal analysis of latch circuitry.

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012

Fig. 4: Positive Feedback Latch Circuit [2]

The expressions for node voltage A and B are as (where gm7 = gm10 & gm8 = gm9):

g m9
I2
I1
g m7

VA =

g m7
g g m2 9

VB =

g m9
g m7
I2
I1
2
g m9
g m9
g

2
m7

And,
2
m7

Both the equation shows that circuits will lead to hysteresis property (if gms of transistors M7 and
M9 are not equal). The large signal (DC) analysis expressions for node voltage at A and B
would be as:
K n7
K n27 K n29

V A = Vtn +

K
I 1 n 9 I 2
K
n7

And,
VB = Vtn +

K n9
K K n29
2
n7

K n7

I 2 I 1
K n9

Here we have expressions for VA and VB in large and small signal analysis, and can see that in
positive feedback configuration (gm7 < gm9) circuit will show hysteresis. From the discussion
above we can see that for proposed design:

(VC Vth )2 =

K n 7 K p5

K p3 K

2
n7

2
n9

K n9
I D 2 I D1
I in I ref +
K n7

..(A)

And,

(VD Vth )2

K n9 K p5

K p3 K

2
n7

2
n9

K n7
I D 2 I D1
I in I ref +
K n9

..(B)

Here both the equations show that proposed circuit will produce hysteresis in output voltage with
respect to applied input currents and hysteresis produced depends on drain current of M2 (ID2).
The exact calculation of hysteresis generated is explained in next section.
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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012

4. CALCULATION OF HYSTERESIS
As we are using positive feedback latch circuit, at the time transitions one of the cross coupled
transistor will go in triode region and so the amount of hysteresis introduced will also depend on
the drain voltages of M8 and M9 (VC and VD respectively).
When current changes from low to high values at the time of switching transistor M8 will
be in triode keeping all other transistors in saturation. So the ratio of drain currents of M5 and M6
can be given by:
I D5
=
I D6

(VC Vtn )2 + K 9 K (2V D 2Vtn VC )VC

(V D Vtn )

7
K9

(V V )2
+
C
tn
K7

=P

As ID5and ID6are mirrored by M3 and M4 respectively, so

I D5 I D3
=
=P
I D6 I D4

Appling KCL at input nodes A and B, we can easily see that

I in = I ref + I D1 PI D 2

Input current in equation (3.36), give the value of current at the time of transition and it can be
referred as transition current (It1).
Same can be done for reversed case; when current changes from high to low values, this time
transistor M9 will go in triode region and input signal current at the time of switching can be
given by (It2):
I in = I ref + I D1 P ' I D 2

Where P ' can be given by,

2
K
(V V )2
V tn ) + 9
tn
K 7 D

P =
(V D V tn )2 + K 9 K (2V C 2Vtn V D )V D
7

(V C

'

So we have transition currents expressions as,

I t1 = I ref + I D1 PI D 2 = I ref + I a

I t 2 = I ref P ' I D 2 I D1 = I ref I b

Equations derived above can be implemented graphically in hysteresis curve as:

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012

Fig. 5: Hysteresis Curve (VC v/s Iin)

Then hysteresis current can be given by
I hy = I t1 I t 2
I hy = P ' I D 2 PI D 2

Equation shows the expression of hysteresis produced by circuit; where we see that it is well
controlled as drain current of M2 (ID2) is always constant (see fig.3 M2 and M4 are diode
connected and no current changing element is available).
Keeping equations (A) and (B) in mind; we see that when all the transistors are in saturation,
amount of hysteresis produced depends on the Ration of Kns. If we set this ratio near to 1; so
that K n 9
I term approximately get cancelled with ID1, and thus amount of hysteresis

K n 7

D2

introduced can nearly be set to zero. This we can understand in other way around that if we
design this circuit in such a way that gms of all the latch transistors be nearly equal ( g m 7 g m 9 or
K n 7 K n 9 ) hysteresis produced can be reduced to zero. As we have already discussed that

hysteresis introduced directly relates with depth of positive feedback (difference of gms), then
this will be the condition when circuit will have a slight positive feedback and so very less
hysteresis. Under such stipulations circuit can also be used as a simple current comparator.

5. SIMULATION RESULTS
For simulation, standard BSIM 0.18m CMOS technology parameters have been used with 3V
power supply. Proposed circuit was designed optimally for speed, power, accuracy and hysteresis.
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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012

Comparator with hysteresis: The design proposed produces hysteresis in output voltage with
respect to the change in direction of input current. DC transfer characteristics observed with
increasing and decreasing values of input currents are shown in Fig. 6 & 7 respectively.

Fig. 6: Hysteresis for Increasing value of Iin (Iref = 0A)

Fig. 7: Hysteresis for Decreasing value of Iin (Iref = 0A)

Here in figures, we see that switching of output occurs at 0.72A (Fig. 6) and -0.65A (Fig. 7)
depending on the direction of change in current. So total amount of hysteresis produced:
I hy = 0.7 A + 0.7 A = 1.4 A

Circuit produces average propagation delay of 0.2ns and 4.8ns for +/- 100A and +/- 1A input
square-wave current pulses respectively, at the DC power consumption of 1.8mW. Transistor
dimensions used are as:

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012

Table 1: Design Parameters: Comparator with Hysteresis

W
L
(Width)
(Length)
0.18m
0.72m
M1, M2
0.54m
0.72m
M3, M4
1.08m
0.18m
M5, M6
0.36m
0.18m
M8, M9
0.27m
0.18m
M7, M10
0.54m
0.18m
Inverter:
PMOS
0.18m
0.18m
Inverter:
NMOS

Comparator without hysteresis: The same design could be extended to comparator without (or
very less) hysteresis in output voltage with the change in direction of input current. DC transfer
characteristics obtained for extended concept with increasing and decreasing values of input
currents are shown in Fig. 8 & 9 respectively.

Fig. 8: Hysteresis for Increasing value of Iin (Iref = 0nA)

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012

Fig. 9: Hysteresis for Decreasing value of Iin (Iref = 0nA)

Here, we see that for this design switching of output doesnt much affected by the direction of
change in current as the transition points are at 9nA (Fig. 8) and -9nA (Fig. 9) with rising and
falling values of input current, respectively. This is just because of very less positive feedback.
Total amount of hysteresis produced:
I hy = 9nA + 9nA = 18nA

Circuit produces average propagation delay of 0.2ns and 1.6ns for +/- 100A and +/- 1A input
square-wave current pulses respectively, at the DC power consumption of 2.3mW. Transistor
dimensions used are as:
Table 2: Design Parameters: Comparator without Hysteresis
W
L
(Width)
(Length)
0.18m
0.72m
M1, M2
0.18m
0.72m
M3, M4
1.19m
0.18m
M5, M6
0.34m
0.18m
M8, M9
0.21m
0.18m
M7, M10
0.54m
0.18m
Inverter:
PMOS
0.18m
0.18m
Inverter:
NMOS

To compare the performance of proposed comparator (without hysteresis case) with existing low
power comparators i.e. Traffs [7], R. Dels [10], L. Chens [14] and V. Kasemsuwans [15],
LTSPICE simulations of all comparators are performed using standard BSIM 0.18m CMOS
technology parameters with 3V power supply.
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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012

Fig. 10: Average Delay (ns): Response to +/- 1A Current Step

Fig. 11: Average Delay (ns): Response to +/- 100A Current Step

6. CONCLUSION
A new current mode comparator with hysteresis is presented. Design have novel structure and
able to achieve crucial parameter of hysteresis control. It is having analogous functionality and
far better performance over the existing one in terms of speed and hysteresis control.
The same design can be extended to a simple current comparator, which compares input signal
and reference currents with high accuracy (less then 50nA), high speed and comparable power
consumption with all existing low power comparators.

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012

ACKNOWLEDGEMENT
I sincerely thank Prof. Chetan Parikh for his valuable guidance in the study of Comparators.

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Authors
Neeraj K. Chasta received his B. Eng. Degree i n Electronics & Communication from
University of Rajasthan, Jaipur, India in 2007, and the M. Tech degree in Information
& Communication Technology with specialization VLSI from Dhirubhai Ambani
institute of Information & Communication Technology (DA-IICT), Gandhinagar,
India in 2010. His current research interests are in analog & mixed signal design with
low power & high speed emphasis & VLSI Testing.

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