5

Common-Source Amplifier
Stage
Twotypes of common-source amplifiers
will be investigated in lab projects. One is with the source grounded and the
other is with a current-source bias (dual power supply). In Units 5.1 and 5.2 we
discuss various aspects of the common-source stage with grounded source, in
Unit 5.3 we take up circuit-linearity considerations, and in Unit 5.4 we cover the
basics of the dual-power-supply amplifier. Both amplifiers are based on the
PMOS, as in the projects. The first two units are mostly a review of the basic
amplifier as presented in previous units, to reinforce the basic concepts. The
PMOS replaces the NMOS (Units 2 and 4) in this unit, to provide familiarity with
the opposite polarity in bias considerations and to illustrate that the linear model
applies in the same manner for both transistor types.

5.1 DC (Bias) Circuit

Dc circuits for the grounded-source amplifier are shown in Fig. 5.1 (PMOS). The
circuit in (a) is based on a single power supply, and the gate bias is obtained with
a resistor voltage-divider network. The circuit in (b) is for a laboratory project
amplifier. Both VGG and VSS are negative, since the source is at ground. There is
no voltage drop across R G since there is negligible gate current. R G is necessary
only to prevent shorting the input signal, Vi. The bias current ID for a given
applied VSG will respond according to (3.8), which is

ID = k p (VSG − Vtpo )2 (1 + λ p VSD )

45
46 Unit 5 Common-Source Amplifier Stage

VGG
Fig. 5.1 Basic PMOS common- R G2
source amplifiers. Single-power- RG
supply amplifier (a) and laboratory Vi Vi
amplifier (b) with VSG (= VGG ) and
VSS controlled by DAQ output Vo
Vo
channels. Note that either end of R G1
the circuit of (a) can be at ground. RD
RD

(a) VSS VSS (b)

The two circuits are equivalent, as VGG and R G of Fig. 5.1.b are the Thévenin
equivalent of the bias network of the Fig. 5.1(a). In the project on the amplifier,
they are actually a voltage and a resistor. This is not a bias-stable circuit, as a
slight change in VSG or the transistor parameters can result in a significant
change in ID. The dual-power-supply circuit of Unit 5.4 is considerably better in
this respect.

5.2 Amplifier Voltage Gain

This dc (bias) circuit becomes an amplifier now simply by adding a signal source
at the gate as in Fig. 5.2. This requires a coupling capacitor, as shown here in the
complete circuit, to prevent disturbing the bias upon connecting the input signal
to the circuit.
In the amplifier of Project 5, the signal will be superimposed on the bias
voltage at the node of VGG . This can be facilitated with LabVIEW and the DAQ. A
capacitor, as in an actual amplifier, is therefore not required. The requirement for
having LabVIEW control over both VGG and VSS, and the limitation of two output
channels, dictates this configuration.
In Project 5 we measure the gain as a function of bias current, ID. For a SPICE
comparison, we need an expression for the gain. For the ideal case, which
neglects the output conductance, gds , the output current is related to the input
voltage by (4.1), which is

I d = gm Vgs = gm Vi
Unit 5.2 Amplifier Voltage Gain 47

VGG

Fig. 5.2 A signal source is connected to RG

the gate through a coupling capacitor.
The capacitor is necessary to isolate the
dc circuit from the signal source.
Vs + Vi
−
Cg
Vo

RD

VSS
The output signal voltage is, in general,

Vds = Vo = −I dR D (5.1)

Vgs -
+
Vi
Fig. 5.3 Signal-equivalent version of the
RG Vo
amplifier stage. Dc nodes are set to zero
volts (circuit reference). The reactance of
Cg is assumed to be zero.
RD gm Vgs

The convention used here for subscript order for signal (linear) variables is
common to the NMOS and PMOS. This is consistent with the fact that the linear
model does not distinguish between the two types. Thus, for example, the dc
terminal voltage for a PMOS is VSG , but the signal equivalent is Vgs (Fig. 5.3) and
the signal input voltage is positive at the input terminal (common-source, gate
input). For the PMOS, iD is defined as positive out of the drain, but the signal
output current is into the drain (as in the NMOS). We note that a positive Vgs
( Vgs = − Vsg ) corresponds to a decrease in the total gate – source voltage, v SG ,
which is consistent with a decrease of iD and positive Id.
48 Unit 5 Common-Source Amplifier Stage

Thus, the negative sign in (5.1) is consistent with the flow of current I d up
through the resistor (Fig. 5.3) for positive Vi = Vgs . The common-source stage is an
inverting amplifier and has an inherent 180o phase shift. From (4.1) and (5.1), the
gain is

Vo
av = = −gmR D (5.2)
Vi

where both Vi = Vgs and Vo = Vds are with respect to ground or the source terminal
for the common-source stage.
If the output resistance, 1 / gds, cannot be neglected (which is the case for the
project on PMOS amplifiers), the transistor current, gm Vi, is shared between the
output resistance and R D. The portion that flows through R D is (Fig. 5.4)

1
I R D = gm Vi (5.3)
1 + g ds R D

Note again that the signal schematic transistor represents a current source with
value g V , as established in connection with Fig. 4.1. The additional feature of
m i

the transistor model is included with the addition of 1/g . This resistance is
ds

actually part of the transistor and is between the drain and source of the
transistor, but the circuit as given is equivalent, as the source is at ground. Since
the output voltage is V = −I D R , the new gain result is
o R D

R
a = −g D
(5.4)
v m
1+g Rsd D

Note that this form evolves from ideal transistor current, gm Vgs , flowing through
the parallel combination of the output resistance and R D.
To facilitate an intuitive grasp of the magnitude of the effect of gds, we use the
expression for g ds (4.13) in (5.4), to obtain

RD
a v = −g m (5.5)
1 + λ p ID R D

Note that IDR D is the voltage drop across RD . For example, for a −10-V power
supply, we choose IDR D ≈ 5 V . A measurement of λp for our devices will show that
Unit 5.2 Amplifier Voltage Gain 49

λp ≈ 1 / 20 V, which results in λpIDR D ≈ 1 / 4. Thus, the effect of g ds ( = λ p ID ) for this

case is significant.

Vi Fig. 5.4 Common-source amplifier stage

g m Vi
signal circuit, with all dc nodes set to zero
volts. The transistor model includes
RG Vo output resistance 1/gds , which appears
directly in parallel with RD with the source
RD 1 / g ds
grounded.

Finally, we can get an overall current dependence for a v with the elimination
of gm , using (4.5) with k ′p ≈ k p, which results in

RD
a v = −2 k p ID (5.6)
1 + λ p IDR D

Using an alternative form for gm (= 2ID / Veffp ) , also (4.5), the gain expression is

ID RD
a v = −2 (5.7)
Veffp 1 + λ p ID R D

where

ID ID
Veffp = ≈
k p (1 + λp VSD ) kp

For simplicity, approximate forms of (4.5) and (4.13) of gm and g ds are used here,
which are independent of VSD. For reference, the “exact” and approximate forms
of (4.5) and (4.13), respectively, are repeated here:

gm = 2 kp (1 + λp VSD )ID ≈ 2 kp ID

and
50 Unit 5 Common-Source Amplifier Stage

ID
g ds = λp ≈ λ p ID
1+ λ p VSD

The “exact” equations of gm and g ds are used in conjunction with the amplifier
projects to compare the computed gain with the measured gain plotted against
I D . This is done in both LabVIEW and Mathcad. Parameters k p and Vtpo (to get

Veffp ) will be extracted from the measured dc data, and λ p will be used as an

adjustable parameter to fit the SPICE and measured gain data.

5.3 Linearity of the Gain of the Common-Source

Amplifier
The connection between I d and Vgs is linear provided that Vgs is small enough, as
considered in the following units. Use of the linear relations also assumes that
the output signal remains in the active region (i.e., neither in the linear region nor
near cutoff). This is discussed below. NMOS subscripts are used. The results are
the same for the PMOS, with a “ p ” subscript substituted for “ n ” and the
subscript order reversed for all bias-voltage variables.

5.3.1 Nonlinearity Referred to the Input

The general equation again is (3.8)

iD = k ′n (v GS − Vtno )2

Then using I d = iD − ID and v GS = VGS + Vgs, the equation for the incremental drain
current becomes

Id = k n′ 2 (VGS − Vtno ) Vgs + Vgs 2  (5.8)

which leads to a nonlinear (variable) transconductance, gm′ , given by

I k n′ (2Veffn Vgs + Vgs 2 )  Vgs 

gm′ = d = = gm  1 ±  (5.9)
Vgs Vgs  2Veffn 
 
Therefore, the condition for linearity is that Vgs << 2Veff , with Veffn = VGS − Vtno
Unit 5.3 Linearity of the Gain of the Common -Source Amplifier 51

and using gm = 2k n′ Veffn .

With this condition not satisfied, an output signal is distorted. However, for
the purpose of measuring the amplifier gain, our signal voltmeter will take the
average of the positive and negative peaks, which is

( ) (
k ′ 2V V + V 2 + k ′n 2Veff Vgs − Vgs 2
I davg = n eff gs gs
) (5.10)
2

In the parabolic relationship, the squared terms cancel entirely. In general,

though, the output signal contains harmonic content (distortion) when Vgs is too
large compared to Veffn.

5.3.2 Nonlinearity Referred to the Output

The discussion above of limits imposed on Vgs assumes that the transistor
remains in the active mode. To clarify this point, reference is made to the output
characteristics of Fig. 5.5. The graph has plots of the output characteristic for
three values of v GS in addition to the load line. The characteristic plot in the
midrange is for no signal. Operating point variables are VDS ≈ 2.5 V and
ID ≈ 40 µA . With a large, positive Vgs , the characteristic moves up to the high-level
plot ( iDhi ) and the opposite occurs for a large but negative Vgs ( iDlo ). The high-
level plot is shown for when the transistor is about to move out of the active
region and into the linear region. Attempts to force v DS to lower values will
create considerable distortion in the output signal voltage. The lower curve
suggests that the positive output signal is on the verge of being cut off (clipped)
for an additional increase in the negative-input signal voltage.
According to the discussion above, the negative signal output voltage is
limited to

Vdsminus = VDS − Veffn (5.11)

Technically, Veffn is from the high-current signal state, but for simplicity, a
reasonable estimate can be made from the dc case; that is, Veffn = VGS − Vtno. The
positive signal limit is

Vdsplus = VDD − VDS = ID R D (5.12

52 Unit 5 Common-Source Amplifier Stage

v effn
iD (µA) iDhi

ID
iDlo
VDS

v DS ( V)
Fig. 5.5 Common-source amplifier stage output characteristics. Output
characteristics are from top to bottom, large high-current signal swing,
iDhi, dc bias, ID, low-current signal swing, i
Dlo. Also shown is the load line.
The current – voltage circuit solution is always the intersection between
a given characteristic and the load line.

The actual output-signal limit is dictated by the smaller of the two for a
symmetrical periodic signal such as a sine-wave. In the example shown in Fig.
5.5, Veffn ≈ 0.5 V, VDS ≈ 2.5 V , and VDD = 5 V . The plus and minus signal-voltage
limits are about 2.5 V and 2.0 V, respectively. Depending on the dc bias, the limit
could be dictated by one or the other. In the amplifier projects, the gain will
typically be measured over a range of dc bias current for a fixed resistor. This
means that for the low-current end of the scan, the signal will be limited by the
magnitude of IDR D and, by design, the plus and minus swings will be made to be
about equal at the highest dc current.
Distortion associated with the nonlinear I d – Vgs relation and that due to
signal limits at the output may be taking place simultaneously. This is seen from
the gain expression (5.7) (g ds = 0)

VRD
av ≈ 2
Veffp

where av ≡ Vds / Vgs and where the approximation is for the case of neglecting the
λ n factor. Thus, for a given Vds , Vgs is
Unit 5.4 Current-Source Common-Source Amplifier: Common-Source Amplifier with a Source Resistor 53

Veffp
Vgs = V (5.13)
2VR D ds

If, for example, Vds is pushed to the positive output-signal limit, then Vds ≈ VR D .
According to (5.13), Vgs = Veffp / 2, and Vgs exceeds the condition for a linear I d –
Vgs relation as given in (5.9),

Id  Vgs 
gm′ = = gm 1 ±
Vgs  2Veffn
 

5.4 Current-Source Common-Source Amplifier:

Common-Source Amplifier with a Source Resistor
The bias circuit of the current-source bias amplifier, shown in Fig. 5.6, has a dual
power supply. One advantage of this is that the input is at zero dc volts such that
the signal can be connected directly without interfering with the bias. The dc
circuit equation for setting up the bias is

VDD − VSG
ID = (5.14)
RS

where (k p′ ≈ k p) VSG ≈ ID / kp + Vtp.

This circuit is more bias stable than the grounded source amplifier, as slight
changes in VSG (due to device parameter variations or temperature) are usually
small compared to VDD . Note that Vtp is used in lieu of Vtpo as VBS ≠ 0. The chip
(CD4007) used in the projects is a p-well device (as noted in Unit 3), with the
NMOS transistors in the well. The well is connected to VSS, while the body of the
chip is connected, as in Fig. 5.6, to VDD . The pn junction formed by the well and
the bulk is thus reverse-biased with a voltage VSS + VDD.
In the amplifier projects, however, we have the latitude to connect the body
and source as there is only one transistor in the circuit and the body can float
along with the source. Thus we can assume that Vtp = Vtpo . As shown in Fig. 5.7,
the signal circuit requires the addition of a bypass capacitor, C s . This places the
source at signal ground provided that the capacitor is large enough. The criterion
54 Unit 5 Common-Source Amplifier Stage

for this is discussed in Unit 6. The voltage-gain equation is the same as in the
amplifier, with the source actually grounded.

VDD

RS
+
Fig. 5.6 Dc circuit of the dual-power- VSG
VDD
supply common-source amplifier. The −
gate is at ground potential, allowing
the signal to be connected directly to RG
the gate. R G is necessary only to prevent VD
shorting out the input signal.
RD
V SS

Without the bypass capacitor, R S is in the signal circuit and a fraction of the
applied signal voltage at the gate is dropped across the resistor. The signal circuit
for this case is shown in Fig. 5.8. The circuit transconductance of the amplifier
with R S was discussed initially in Unit 4. This is reviewed in the following.

VDD

RS
Fig. 5.7 Amplifier circuit with a
bypass capacitor attached between
the source and ground to tie the Cs
source to signal ground. Signal input
is attached directly to the gate. Body +
Vi = Vg Vo
and source are connected internally in − RG
the project chip for the transistor used
in the amplifier. RD

VSS

An applied input signal, Vi = Vg, divides between the gate – source terminals
and the source resistor according to [(4.6)]

Vg = Vgs + I dR S
Unit 5.5 Design of a Basic Common-Source Amplifier 55

RS
Vgs -
Fig. 5.8 Signal circuit for dual-power
supply common-source amplifier. Input +
signal voltage, V , is divided between Vgs,
i

+
the control voltage, and the source Vi = Vg RG Vo
resistor according to the ratio 1 : gmRS . −

RD

When combing this with I d = gm Vgs , we obtain [(4.7)]

Id
Vg = Vgs + gm VgsR S = (1 + gmR S ) Vgs = (1 + gmR S )
gm

The circuit transconductance, Gm , is then [(4.8)]

Id gm
Gm = =
Vg 1 + gmR S

The gain for this case is thus (neglecting g ds )

Vd g R
av = = −GmR D = − m D (5.15)
Vg 1 + g mR S

In one of the amplifier projects, R S = R D , and the gain without the bypass
capacitor is actually less than unity.

5.5 Design of a Basic Common-Source Amplifier

Unlike in the laboratory environment, an actual practical common-source
amplifier would have a single power supply for the base and collector circuit
bias. Also, the circuit design requires a tolerance to a wide range of parameter
56 Unit 5 Common-Source Amplifier Stage

variation, including that due to temperature change. In this unit, the design
process for a possible common-source amplifier is discussed. Emphasis is on dc
bias stability, that is, on tolerance to device parameter and circuit component
variations.
The common-source amplifier to be designed is shown in Fig. 5.9. Source
resistor, R S, is included for bias (and gain) stabilization. The goal is for the circuit
to function properly for any NMOS transistor, which has device parameters k n
and Vtno that fall into a wide range of values, as is normally expected. Tolerance
to component variation, such as resistor values, could also be built into the
design.
VDD

Fig. 5.9 NMOS common-source amplifier RD

R G1
with R S for bias and gain stabilization. Gate
bias is provided by a voltage-divider
Cg Vo
network consisting of R G1 and R G2 . The body
Vi
and source terminals are connected. Cs

R G2
RS

Gate voltage VG is provided by the voltage divider, consisting of resistors R G1

and R G2. Since there is no gate current, the gate bias voltage is [(1.2)]

R G2
VG = V
R G 2 + R G1 DD

Voltage VG is thus relatively stable and can be considered constant. Once VG has
been established, the drain current will be dictated by

VG − VGS
ID = (5.16)
RS

Since the gate – source voltage is given by

Unit 5.5 Design of a Basic Common-Source Amplifier 57

ID
VGS = + Vtno (5.17)
kn

the drain current, ID, may be expressed in terms of the device parameters as

ID
VG − − Vtno
kn
ID = (5.18)
RS

This result reveals the dependence of ID on the magnitudes of k n and Vtno.

(Again, for simplicity, as in the amplifier projects, we will assume that the body
and source are connected such that Vtn = Vtno .)
Bias current ID is assumed to be a given. The initial design then is conducted
for the NMOS nominal, average values for k n and Vtno . Any combination of VG
and R S that satisfies (5.18) will provide the design ID . Specific values for VG and
R S will be dictated by stability requirements. Suppose that k n is expected to fall
within k no ± δk n and Vtno within Vtnoo ± δVtno, where k no and Vtnoo are the nominal
values of the original design. Assume that the design bias current associated with
k no and Vtnoo is IDo. At the extremes for the parameters, the low and high currents
will be

ID
VG − − ( Vtnoo ± δVtno )
k no ∓ δk n
IDlo,Dhi = (5.19)
RS

Resistor R S, for the given VG and design drain current, is

VG − VGSo
RS = (5.20)
IDo

VGSo is obtained from (5.17), using the nominal parameter values. The low and
high current limits tend to converge on VG /R S as VG becomes large. That is, in the
limit, VG dominates the voltages in the numerator of (5.19), thus rendering the
expression insensitive to the minor contributions from changes in k n and Vtno .
An important design consideration is drain – source voltage, VDS , as this
dictates the output signal range. This is calculated from
58 Unit 5 Common-Source Amplifier Stage

VDS = VDD − ID (R D + R S ) (5.21)

In the design of the amplifier, drain resistor R D is normally selected for equal
positive and negative peak-signal maximums. This configuration is illustrated in
Fig. 5.10, which shows the output characteristic of the transistor in the circuit.
The signal is limited by VDD − VR S and Veffno = VGSo − Vtno at the high and low ends
of the voltage range, respectively. Therefore, nominal bias should be set at

VDD − IDoR S + Veffno

VDSo = (5.22)
2

For simplicity, it is assumed that v effn ≈ Veffno. Veffno, VDDo, and IDo are the bias
values at the nominal parameter values. The bias drain voltage is VDSo plus the
drop across R S, that is,

VDo = VDSo + IDoR S (5.23)

Knowing VDo then provides for the calculation of R D from

VDD − VDo
RD = (5.24)
I Do

where VDo and IDo are for the initial design with k no and Vtnoo .
An optimization design sequence plots the limits for a range of VG and for
specified δVtno and δk n. An example is shown in Fig. 5.11. The plot of VDSo
corresponds to the nominal k no and Vtnoo. The curve slopes downward as IDR S
increases for increasing VG at constant nominal bias current, IDo. VDShi is for the
combination of δVtno and δk n, which gives the maximum positive deviation from
the nominal, and VDSlo is the opposite. The example of Fig. 5.11 is for VDD = 10 V
and design bias current of I Do = 100 µA and nominal parameters k no = 300 µA / V 2,
Vtnoo = 1.5 V, δVtno = 0.1 V , and δk n = 100 µA / V 2. Experience with the CMOS chip of
our amplifier project (Project 7) indicates that these are representative.
Figure 5.12 shows plots of the computed positive and negative signal-peak
limits. Due to the increasing VR with increasing VG, the signal range decreases, as
S

shown by the plots. Thus, the signal-peak limits have a maximum, as is evident
in the graph. The design of the amplifier uses VG at the maximum of the lower
Unit 5.5 Design of a Basic Common-Source Amplifier 59

curve. The value of VG is consistent with the maximum VDSlo in the plot of Fig.
5.11. In the example, VG ≈ 3 V.

v effn

iD (µA) iR D iDsig

ID
iR D + R S

VDS

v DS ( V) VDD − IDR S
Fig. 5.10 Output characteristic of the transistor of the amplifier with
bias VDS set approximately according to (5.22). The signal is restricted
within the range VDD − VR S and approximately v effn . The characteristic
curves are for no signal (solid plot) and for the signal at a maximum
(dashed plot), as limited by the transistor going into the inactive (linear)
region. The load lines are dc (solid line) and signal (ac, dashed line).

Once VG is determined, the selection of R G1 is made from (1.2), which is

R G2 R
VG = V = G V
R G2 + R G1 DD R G1 DD

where R G is the parallel combination

R G2 R G1
RG =
R G2 + R G1

R G can be selected somewhat arbitrarily but could be dictated by the coupling

capacitor, Cg, requirement. Associated with the coupling capacitor is the 3 - dB
frequency (6.2), which is
60 Unit 5 Common-Source Amplifier Stage

1
f3dB =
2πR G C g

VDShi

VDSo

VDSlo

VG
Fig. 5.11 Computed high and low range of VDS as a function of gate-bias
voltage VG. The computation is with kno = 300 µA / V2 , Vtnoo = 1.5 V, δVtno = 0.1 V,
and δk n = 100 µA / V2.

R G2 is then calculated from

R G1R G
R G2 =
R G1 − R G

The gain equations for the circuit of Fig. 5.9, with and without a bypass capacitor,
are (5.2) and (5.15), respectively. These are

a v = −gm R D

and

gmR D
av = −
1 + gm R S

In the design procedure outlined in this unit, emphasis is on stability and the
gain falls out. This would typically be the case for this type of amplifier. We note
that due to the characteristically small gm of MOSFETs, the voltage gain is
Unit 5.5 Design of a Basic Common-Source Amplifier 61

relatively small. Gain can be improved considerably through the use a current-
source load, as in the amplifier of Unit 10.

Vdplus
Vdplus
Vdminus

Vd min us

VG
Fig. 5.12 Computed maximums for negative and positive output voltage
signal peaks as a function of VG: Vdplus , positive maximum; Vdminus, negative
maximum.
62 Unit 5 Common-Source Amplifier Stage

5.6 Summary of Equations

a v = −gm R D Common-source amplifier-stage voltage gain.
RD Common-source amplifier gain including
a v = −g m
1 + λ p ID R D output resistance, PMOS. (Same for NMOS
with λn.)
 Vgs  Nonlinear transconductance for large input
gm′ = gm  1 ±  signals. (Same for PMOS with Veffp .)
 2Veffn 
 
Vdsminus = VDS − Veffn Negative output signal limit, NMOS.
Vdsminus = VSD − Veffp Negative output signal limit, PMOS.
Vdsplus = VDD − VDS = ID R D Positive output signal limit, NMOS.
Vdsplus = VSS − VSD = ID R D Positive output signal limit, PMOS.
g R Voltage gain of common-source stage with
av = − m D
1 + gm R S source resistor.
gm Circuit transresistance of common-source stage
Gm =
1 + g mR S with source resistor.

5.7 Exercises and Projects

Project Mathcad Files Exercise05.mcd - Project05.mcd

Laboratory Project 5 PMOS Common-Source Amplifier

P5.2 PMOS Common-Source Amplifier DC Setup

P5.3 Amplifier Gain at One Bias Current

P5.4 Amplifier Gain versus Bias Current