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    Testbencch RISC32

    Uploaded by

    Jonathan Arley Torres Castañeda
    This document contains the source code for a testbench module that simulates a PicoRV32 CPU core. It defines modules for the testbench, CPU wrapper, memory, and CPU itself. The testbench drives a clock and resets the system. It initializes memory from a firmware file. It checks for traps from the CPU and finishes simulation after a timeout. The wrapper connects the CPU and memory modules. The memory module implements an AXI interface to simulate external memory. It reads/writes data from an internal array. The CPU module contains the PicoRV32 core implementation.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd

    Testbencch RISC32

    Uploaded by

    Jonathan Arley Torres Castañeda
    57 views7 pages
    This document contains the source code for a testbench module that simulates a PicoRV32 CPU core. It defines modules for the testbench, CPU wrapper, memory, and CPU itself. The testbench drives a clock and resets the system. It initializes memory from a firmware file. It checks for traps from the CPU and finishes simulation after a timeout. The wrapper connects the CPU and memory modules. The memory module implements an AXI interface to simulate external memory. It reads/writes data from an internal array. The CPU module contains the PicoRV32 core implementation.

    Original Description:

    TestbenchRisc32

    Original Title

    testbencchRISC32

    Copyright

    © © All Rights Reserved

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    This document contains the source code for a testbench module that simulates a PicoRV32 CPU core. It defines modules for the testbench, CPU wrapper, memory, and CPU itself. The testbench drives a clock and resets the system. It initializes memory from a firmware file. It checks for traps from the CPU and finishes simulation after a timeout. The wrapper connects the CPU and memory modules. The memory module implements an AXI interface to simulate external memory. It reads/writes data from an internal array. The CPU module contains the PicoRV32 core implementation.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Download as txt, pdf, or txt
    57 views7 pages

    Testbencch RISC32

    Uploaded by

    Jonathan Arley Torres Castañeda
    This document contains the source code for a testbench module that simulates a PicoRV32 CPU core. It defines modules for the testbench, CPU wrapper, memory, and CPU itself. The testbench drives a clock and resets the system. It initializes memory from a firmware file. It checks for traps from the CPU and finishes simulation after a timeout. The wrapper connects the CPU and memory modules. The memory module implements an AXI interface to simulate external memory. It reads/writes data from an internal array. The CPU module contains the PicoRV32 core implementation.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
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    You are on page 1of 7

    //

    //
    //
    //
    //
    //

    This is free and unencumbered software released into the public domain.
    Anyone is free to copy, modify, publish, use, compile, sell, or
    distribute this software, either in source code form or as a compiled
    binary, for any purpose, commercial or non-commercial, and by any
    means.

    `timescale 1 ns / 1 ps
    `ifndef VERILATOR
    module testbench #(
    parameter AXI_TEST = 0,
    parameter VERBOSE = 0
    );
    reg clk = 1;
    reg resetn = 0;
    always #5 clk = ~clk;
    initial begin
    repeat (100) @(posedge clk);
    resetn <= 1;
    end
    initial begin
    if ($test$plusargs("vcd")) begin
    $dumpfile("testbench.vcd");
    $dumpvars(0, testbench);
    end
    repeat (1000000) @(posedge clk);
    $display("TIMEOUT");
    $finish;
    end
    picorv32_wrapper #(
    .AXI_TEST (AXI_TEST),
    .VERBOSE (VERBOSE)
    ) top (
    .clk
    (clk ),
    .resetn (resetn)
    );
    endmodule
    `endif
    module picorv32_wrapper #(
    parameter AXI_TEST = 0,
    parameter VERBOSE = 0
    ) (
    input clk,
    input resetn
    );
    wire
    trap;
    reg [31:0] irq;
    always @* begin
    irq = 0;
    irq[4] = &uut.picorv32_core.count_cycle[12:0];
    irq[5] = &uut.picorv32_core.count_cycle[15:0];

    end
    wire
    mem_axi_awvalid;
    wire
    mem_axi_awready;
    wire [31:0] mem_axi_awaddr;
    wire [ 2:0] mem_axi_awprot;
    wire
    mem_axi_wvalid;
    wire
    mem_axi_wready;
    wire [31:0] mem_axi_wdata;
    wire [ 3:0] mem_axi_wstrb;
    wire
    wire

    mem_axi_bvalid;
    mem_axi_bready;

    wire
    mem_axi_arvalid;
    wire
    mem_axi_arready;
    wire [31:0] mem_axi_araddr;
    wire [ 2:0] mem_axi_arprot;
    wire
    mem_axi_rvalid;
    wire
    mem_axi_rready;
    wire [31:0] mem_axi_rdata;
    axi4_memory #(
    .AXI_TEST (AXI_TEST),
    .VERBOSE (VERBOSE)
    ) mem (
    .clk
    (clk
    .mem_axi_awvalid (mem_axi_awvalid
    .mem_axi_awready (mem_axi_awready
    .mem_axi_awaddr (mem_axi_awaddr
    .mem_axi_awprot (mem_axi_awprot
    .mem_axi_wvalid
    .mem_axi_wready
    .mem_axi_wdata
    .mem_axi_wstrb

    (mem_axi_wvalid
    (mem_axi_wready
    (mem_axi_wdata
    (mem_axi_wstrb

    ),
    ),
    ),
    ),
    ),
    ),
    ),
    ),
    ),

    .mem_axi_bvalid (mem_axi_bvalid ),
    .mem_axi_bready (mem_axi_bready ),
    .mem_axi_arvalid
    .mem_axi_arready
    .mem_axi_araddr
    .mem_axi_arprot

    (mem_axi_arvalid
    (mem_axi_arready
    (mem_axi_araddr
    (mem_axi_arprot

    ),
    ),
    ),
    ),

    .mem_axi_rvalid (mem_axi_rvalid ),
    .mem_axi_rready (mem_axi_rready ),
    .mem_axi_rdata (mem_axi_rdata )
    );
    picorv32_axi #(
    `ifdef SP_TEST
    .ENABLE_REGS_DUALPORT(0),
    `endif
    `ifdef COMPRESSED_ISA
    .COMPRESSED_ISA(1),
    `endif
    .ENABLE_MUL(1),

    .ENABLE_DIV(1),
    .ENABLE_IRQ(1)
    ) uut (
    .clk
    (clk
    ),
    .resetn
    (resetn
    ),
    .trap
    (trap
    ),
    .mem_axi_awvalid(mem_axi_awvalid),
    .mem_axi_awready(mem_axi_awready),
    .mem_axi_awaddr (mem_axi_awaddr ),
    .mem_axi_awprot (mem_axi_awprot ),
    .mem_axi_wvalid (mem_axi_wvalid ),
    .mem_axi_wready (mem_axi_wready ),
    .mem_axi_wdata (mem_axi_wdata ),
    .mem_axi_wstrb (mem_axi_wstrb ),
    .mem_axi_bvalid (mem_axi_bvalid ),
    .mem_axi_bready (mem_axi_bready ),
    .mem_axi_arvalid(mem_axi_arvalid),
    .mem_axi_arready(mem_axi_arready),
    .mem_axi_araddr (mem_axi_araddr ),
    .mem_axi_arprot (mem_axi_arprot ),
    .mem_axi_rvalid (mem_axi_rvalid ),
    .mem_axi_rready (mem_axi_rready ),
    .mem_axi_rdata (mem_axi_rdata ),
    .irq
    (irq
    )
    );
    reg [1023:0] firmware_file;
    initial begin
    if(!$value$plusargs("firmware=%s", firmware_file))
    firmware_file = "firmware/firmware.hex";
    $readmemh(firmware_file, mem.memory);
    end
    integer cycle_counter;
    always @(posedge clk) begin
    cycle_counter <= resetn ? cycle_counter + 1 : 0;
    if (resetn && trap) begin
    `ifndef VERILATOR
    repeat (10) @(posedge clk);
    `endif
    $display("TRAP after %1d clock cycles", cycle_counter);
    $finish;
    end
    end
    endmodule
    module axi4_memory #(
    parameter AXI_TEST = 0,
    parameter VERBOSE = 0
    ) (
    input
    clk,
    input
    mem_axi_awvalid,
    output reg
    mem_axi_awready = 0,
    input [31:0]
    mem_axi_awaddr,
    input [ 2:0]
    mem_axi_awprot,
    input
    output reg
    input [31:0]
    input [ 3:0]

    mem_axi_wvalid,
    mem_axi_wready = 0,
    mem_axi_wdata,
    mem_axi_wstrb,

    output reg
    input

    mem_axi_bvalid = 0,
    mem_axi_bready,

    input
    output reg
    input [31:0]
    input [ 2:0]

    mem_axi_arvalid,
    mem_axi_arready = 0,
    mem_axi_araddr,
    mem_axi_arprot,

    output
    mem_axi_rvalid = 0,
    input
    mem_axi_rready,
    output reg [31:0] mem_axi_rdata
    );
    reg [31:0] memory [0:64*1024/4-1] /* verilator public */;
    reg verbose;
    initial verbose = $test$plusargs("verbose") || VERBOSE;
    reg axi_test;
    initial axi_test = $test$plusargs("axi_test") || AXI_TEST;
    reg [63:0] xorshift64_state = 64'd88172645463325252;
    task xorshift64_next;
    begin
    // see page 4 of
    t RNGs". Journal of Statistical Software
    xorshift64_state
    << 13);
    xorshift64_state
    >> 7);
    xorshift64_state
    << 17);
    end
    endtask

    Marsaglia, George (July 2003). "Xorshif


    8 (14).
    = xorshift64_state ^ (xorshift64_state
    = xorshift64_state ^ (xorshift64_state
    = xorshift64_state ^ (xorshift64_state

    reg [2:0] fast_axi_transaction = ~0;


    reg [4:0] async_axi_transaction = ~0;
    reg [4:0] delay_axi_transaction = 0;
    always @(posedge clk) begin
    if (axi_test) begin
    xorshift64_next;
    {fast_axi_transaction, async_axi_transaction, de
    lay_axi_transaction} <= xorshift64_state;
    end
    end
    reg latched_raddr_en = 0;
    reg latched_waddr_en = 0;
    reg latched_wdata_en = 0;
    reg fast_raddr = 0;
    reg fast_waddr = 0;
    reg fast_wdata = 0;
    reg
    reg
    reg
    reg

    [31:0]
    [31:0]
    [31:0]
    [ 3:0]

    latched_raddr;
    latched_waddr;
    latched_wdata;
    latched_wstrb;

    reg

    latched_rinsn;

    task handle_axi_arvalid; begin


    mem_axi_arready <= 1;
    latched_raddr = mem_axi_araddr;
    latched_rinsn = mem_axi_arprot[2];
    latched_raddr_en = 1;
    fast_raddr <= 1;
    end endtask
    task handle_axi_awvalid; begin
    mem_axi_awready <= 1;
    latched_waddr = mem_axi_awaddr;
    latched_waddr_en = 1;
    fast_waddr <= 1;
    end endtask
    task handle_axi_wvalid; begin
    mem_axi_wready <= 1;
    latched_wdata = mem_axi_wdata;
    latched_wstrb = mem_axi_wstrb;
    latched_wdata_en = 1;
    fast_wdata <= 1;
    end endtask
    task handle_axi_rvalid; begin
    if(verbose)
    $display("RD: ADDR=%08x DATA=%08x%s", latched_raddr, mem
    ory[latched_raddr >> 2], latched_rinsn ? " INSN" : "");
    if (latched_raddr < 64*1024) begin
    mem_axi_rdata <= memory[latched_raddr >> 2];
    mem_axi_rvalid <= 1;
    latched_raddr_en = 0;
    end else begin
    $display("OUT-OF-BOUNDS MEMORY READ FROM %08x", latched_
    raddr);
    $finish;
    end
    end endtask
    task handle_axi_bvalid; begin
    if (verbose)
    $display("WR: ADDR=%08x DATA=%08x STRB=%04b", latched_wa
    ddr, latched_wdata, latched_wstrb);
    if (latched_waddr < 64*1024) begin
    if (latched_wstrb[0]) memory[latched_waddr >> 2][ 7: 0]
    <= latched_wdata[ 7: 0];
    if (latched_wstrb[1]) memory[latched_waddr >> 2][15: 8]
    <= latched_wdata[15: 8];
    if (latched_wstrb[2]) memory[latched_waddr >> 2][23:16]
    <= latched_wdata[23:16];
    if (latched_wstrb[3]) memory[latched_waddr >> 2][31:24]
    <= latched_wdata[31:24];
    end else
    if (latched_waddr == 32'h1000_0000) begin
    if (verbose) begin
    if (32 <= latched_wdata && latched_wdata < 128)
    $display("OUT: '%c'", latched_wdata[7:0]
    );
    else

    $display("OUT: %3d", latched_wdata);


    end else begin
    $write("%c", latched_wdata[7:0]);
    `ifndef VERILATOR
    $fflush();
    `endif
    end
    end else begin
    $display("OUT-OF-BOUNDS MEMORY WRITE TO %08x", latched_w
    addr);
    $finish;
    end
    mem_axi_bvalid <= 1;
    latched_waddr_en = 0;
    latched_wdata_en = 0;
    end endtask
    always @(negedge clk) begin
    if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && asyn
    c_axi_transaction[0]) handle_axi_arvalid;
    if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && asyn
    c_axi_transaction[1]) handle_axi_awvalid;
    if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && asyn
    c_axi_transaction[2]) handle_axi_wvalid;
    if (!mem_axi_rvalid && latched_raddr_en && async_axi_transaction
    [3]) handle_axi_rvalid;
    if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && a
    sync_axi_transaction[4]) handle_axi_bvalid;
    end
    always @(posedge clk) begin
    mem_axi_arready <= 0;
    mem_axi_awready <= 0;
    mem_axi_wready <= 0;
    fast_raddr <= 0;
    fast_waddr <= 0;
    fast_wdata <= 0;
    if (mem_axi_rvalid && mem_axi_rready) begin
    mem_axi_rvalid <= 0;
    end
    if (mem_axi_bvalid && mem_axi_bready) begin
    mem_axi_bvalid <= 0;
    end
    if (mem_axi_arvalid && mem_axi_arready && !fast_raddr) begin
    latched_raddr = mem_axi_araddr;
    latched_rinsn = mem_axi_arprot[2];
    latched_raddr_en = 1;
    end
    if (mem_axi_awvalid && mem_axi_awready && !fast_waddr) begin
    latched_waddr = mem_axi_awaddr;
    latched_waddr_en = 1;
    end
    if (mem_axi_wvalid && mem_axi_wready && !fast_wdata) begin
    latched_wdata = mem_axi_wdata;

    latched_wstrb = mem_axi_wstrb;
    latched_wdata_en = 1;
    end
    if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && !del
    ay_axi_transaction[0]) handle_axi_arvalid;
    if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && !del
    ay_axi_transaction[1]) handle_axi_awvalid;
    if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && !del
    ay_axi_transaction[2]) handle_axi_wvalid;
    if (!mem_axi_rvalid && latched_raddr_en && !delay_axi_transactio
    n[3]) handle_axi_rvalid;
    if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && !
    delay_axi_transaction[4]) handle_axi_bvalid;
    end
    endmodule

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