Carry-Propagate Adder

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Carry-Propagate Adder

Connecting full-adders to make a multi-bit carry-propagate adder:

Right-most adder adds least-significant bits. Carry-out is passed


to next adder, which adds it to the next-most significant bits, etc.
Can extend this to any number of bits
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Carry-LookAhead Adders
By pre-computing the major part of each carry equation, we can make a
much faster adder.
We start by computing the partial results (for each bit):
pi = ai + bi
gi = ai bi

(called "propagate term")


(called the "generate term")

Then:
ci+1 = gi + pi ci

(carry_out from bit i)

We can compute these for each bit independently (no ripple)


Each of the carries can now be expressed in terms of p and g:
ci+2 = gi+1 + pi+1 ci+1 (carry_from bit i+1)
ci+3 = gi+2 + pi+2 ci+2 (carry_from bit i+2)
ci+4 = gi+3 + pi+3 ci+3 (carry_from bit i+3)
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Carry-LookAhead Adders
Now, by forward substitution (show this and check for errors!)

ci+1 = gi + pi ci
ci+2 = gi+1 + pi+1 gi + pi+1 pi ci
ci+3 = gi+2 + pi+2 gi+1 + pi+2 pi+1 gi + pi+2 pi+1 pi ci
ci+4 = gi+3 + pi+3 gi+2 + pi+3 pi+2 gi+1 + pi+3 pi+2 pi+1 gi +
pi+3 pi+2 pi+1 pi ci
So we can express each carry as a function of generate and
propagate signals; in a two level AND-OR circuit and without any
ripple effect!

A3 B3

A2 B2

A1 B1

A0 B0

p/g generator (simple and/or gates)

P3 G3

C4

P2 G2

P1 G1

P0 G0

carry generator (a bit more complex but


still only AND/OR gates)
C3

C2

C1

A3 B3

A2 B2

A1 B1

A0 B0

FA

FA

FA

FA

S3

S2

C0

S1

S0
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Hierarchical Carry-LookAhead Adders


Theoretically, we could create a carry-lookahead adder for any N
But these equations are complex. It is unreasonable to extend
this to beyond more than 4 bits or so. Why?
Can combine carry look-ahead and carry-propagate schemes:

Multipliers
Consider a 1 bit x 1 bit multiplier:

Multiplication of two bits is simply an AND gate

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Multipliers
One bit number x N-bit number
eg. 10111011 x 1 = 10111011
10111011 x 0 = 00000000
B(3:0)

A x B(3:0)

A
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Multipliers
N bit x N bit number (consider 4x4):

S7

Y3X3
S6

Y2X3
Y3X2
S5

Y1X3
Y2X2
Y3X1
S4

X3
Y3
Y0X3
Y1X2
Y2X1
Y3X0
S3

X2
Y2
Y0X2
Y1X1
Y2X0

X1
Y1
Y0X1
Y1X0

X0
Y0
Y0X0

S2

S1

S0

This would require 16 AND gates and a 8 bit, 4 input adder,


and lots of wiring (wiring is becoming a big problem in
integrated circuits).

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Multipliers
We can reduce the wiring by distributing the adder:

S34

S24
Y3X3
S33

S14
Y2X3
S23
Y3X2
S32

Y1X3
S13
Y2X2
S22
Y3X1
S31

X3
Y3
Y0X3
Y1X2
S12
Y2X1
S21
Y3X0
S30

P7

P6

P5

P4

P3

X2
Y2
Y0X2
Y1X1
S11
Y2X0
S20

X1
Y1
Y0X1
Y1X0
S10

X0
Y0
Y0X0

P2

P1

P0

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Multipliers
Recall: Half-Adder vs. Full-Adder:

By combining half-adders, full-adders, and AND gates, we can


implement our array multiplier

14

Multipliers

15

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